NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 274

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.11.10
274
DIO[1:0]SQUELCH_CNT: PCIe Cluster Squelch Count
Device:
Function: 0
Offset:
15:12
9:0
Bit
11
10
RWST
RWST
Attr
RV
RV
4, 0
396h
Default
164h
1h
1h
0h
Reserved
Dis_Rx_L1L0s_idle: Disable automatic shutoff of receivers during L1.Idle/
L0s.Idle power states
1: Disable automatic shut off of receivers during L1 or L0s idle power state entry.
(default).
0: Enables Rx shut off. This bit when clear forces the hardware to shut off the
Receiver side in BNB during the L0s/L1 power states.
Note:
DIS_LANE_LANE_DESKEW: Disable Lane to Lane Deskew
1: Lane to lane deskew is disabled. Should be set before IBIST is started and
cleared after IBIST is stopped
0: Normal link operation. i.e Lane to lane deskew is enabled (default)
Reserved
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
This bit is functional in MCH steppings B3 and newer. Refer to erratum 19
(501621).
§
Description
Register Description