NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 275

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

System Address Map
4
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
System Address Map
The Intel 5000P Chipset supports 36 bits of memory address space. Internally Intel
5000P Chipset carries 40 bits of address into various memory controller components.
The processors designed for Intel 5000P Chipset, support only 36 bits of memory
addressing and 16 bits of addressable I/O space. However internally the MCH supports
40 bits and several of the MCH memory configuration registers require 40 bit address
programming.
There is a legacy (compatibility) memory address space under the 1-MB region that is
divided into regions that can be individually controlled with programmable attributes
(for example, disable, read/write, write only, or read only). Attribute programming is
described in Chapter 3. The Intel 5000P Chipset supports several fixed address ranges
in addition to the compatibility range. These are:
There are several relocatable regions such as the memory mapped I/O region.These
regions are controlled by various programmable registers covered in Chapter 3.
This chapter focuses on how the memory space is partitioned and the uses of the
separate memory regions.
In the following sections, it is assumed that all of the compatibility memory ranges
reside on the ESI/PCI Express/PCI interfaces. VGA address ranges are mapped to PCI
Express address space as well. In the absence of more specific references, cycle
descriptions referencing PCI should be interpreted as the ESI/PCI interface.
The Intel 5000P Chipset memory map includes a number of programmable ranges. All
of these ranges must be unique and non-overlapping as shown in
no hardware interlocks to prevent problems in the case of overlapping ranges. Accesses
to overlapped ranges may produce indeterminate results. For example, setting
HECBASE to all zeros will overlap the MMCFG region and the compatibility region
resulting in unpredictable results.
• Compatibility area below 1MB
• Interrupt delivery region
• System region in 32MB just below 4GB
Figure
4-1. There are
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