NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 276

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Figure 4-1.
4.1
4.1.1
276
System Memory Address Map
System Memory Address Ranges
The Intel 5000P Chipset platform supports 36 bits (64 GB) of physical memory Or
maximum of 40-bit system address with up to 64 GB or physical memory support.
Other address spaces supported by the Intel 5000P Chipset are:
The chipset treats accesses to various address ranges in different ways. There are fixed
ranges like the compatibility region below 1 MB, and variable ranges like the memory
mapped I/O range. The locations of these ranges in the memory map are illustrated in
Figure
32/64-bit addressing
For inbound and outbound writes and reads, the Intel 5000P Chipset MCH supports 64-
bit address format. If an outbound transaction’s address is a 32-bit address, the Intel
5000P Chipset MCH will issue the transaction with a 32-bit addressing format on PCI
Express. Only when the address requires more than 32 bits will the Intel 5000P Chipset
MCH initiate transactions with 64-bit address format. It is the responsibility of the
software to ensure that the relevant bits are programmed for 64-bits based on the OS
limits. (for example, 40-bits for Intel 5000P Chipset MCH).
• 36-bit local address supported over the FB-DIMM channels for physical memory
• 32 and 64 bit address bit formats supported for PCI Express interfaces.
space.
Top of the Physical
DRAM Memory
4-2.
64 GB
0
PCI-E/PCI-X/PCI
Memory Address
Address Range
Main Memory
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Range
Graphics
Memory
Independently Programmable Non-
Overlapping Memory Windows
AGP Address
Range
Graphics (AGP)
System Address Map
Aperture