NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 279

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

System Address Map
4.2.2
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Legacy VGA Ranges (A 0000h–B FFFFh)
The 128 KB Video Graphics Adapter Memory range (A 0000h to B FFFFh) can be
mapped to the VGA device which may be on any PCI Express or ESI port, or optionally
it can be mapped to main memory (it must be mapped to SMM space). Mapping of this
region is controlled by the VGA steering bits. At power on this space is mapped to the
ESI port.
Priority for VGA mapping is constant in that the MCH consistently decodes internally
mapped devices first. The MCH positively decodes internally mapped devices. This
region can be redirected by BIOS to point to any bus which has a VGA card. If the
VGAEN bit is set in one of the Intel 5000P Chipset MCH.BCTRL configuration registers
associated with the PCI Express port, then transactions in this space are sent to that
PCI Express port.
The VGAEN bit can only be set in one and only one of the Intel 5000P Chipset
MCH.BCTRL registers. If any VGAEN bits are set, all the ISAEN bits must be set. If the
VGAEN bit of a PCI Express port x in the Intel 5000P Chipset MCH is set and
BCTRL[x].VGA16bdecode is set to zero, then ISAEN bits of all peer PCI Express ports
with valid I/O range (PCICMD.IOAE = 1, IOLIMIT >= IOBASE) in the MCH must be set
by software. Otherwise, it is a programming error due to the resulting routing conflict.
If the VGAEN bit of a PCI Express port x in the MCH is set, and
BCTRL[x].VGA16bdecode is set to one, and if there is another PCI Express port y (x !=
y) with valid I/O range including the lowest 4K I/O addresses (PCICMD[y].IOAE = 1,
IOLIMIT[y] >= IOBASE[y] = 0000h), BCTRL[y].ISAEN bit must be set to one by
software. Otherwise, it is a programming error.
This region is non-cacheable.
Compatible SMRAM Address Range (A 0000h–B FFFFh)
The legacy VGA range may also be used for mapping SMM space. The SMM range (128
KB) can overlay the VGA range in the A and B segments. If the SMM range overlaps an
enabled VGA range then the state of the SMMEM# signal determines where accesses to
the SMM Range are directed. SMMEM# is a special FSB message bit that uses
multiplexed address bit FSBxA[7]#. SMMEM# is valid during the second half of the FSB
request phase clock. (the clock in which FSBxADS# is driven asserted).
SMMEM# asserted directs the accesses to the memory and SMMEM# deasserted
directs the access to the PCI Express bus where VGA has been mapped.
When compatible SMM space is enabled, SMM-mode processor accesses to this range
are routed to physical system DRAM at this address. Non-SMM-mode processor
accesses to this range are considered to be to the video buffer area as described above.
Graphics port and ESI originated cycles to enabled SMM space are not allowed and are
considered to be to the Video Buffer Area.
Monochrome Adapter (MDA) Range (B 0000h–B 7FFFh)
The Intel 5000P Chipset does not support this range.
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