NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 28

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

28
FSB0DP[3:0]#
FSB0DRDY#
FSB0DSTBP[3:0]#
FSB0DSTBN[3:0]#
FSB0HIT#
FSB0HITM#
FSB0LOCK#
FSB0MCERR#
FSB0REQ[4:0]#
FSB0RESET#
FSB0RS[2:0]#
FSB0RSP#
FSB0TRDY#
FSB0VREF
Signal Name
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
Analog
Type
Processor 0 Data Bus Parity: FSB0DP[3:0]# provide parity protection on
the data bus.
Processor 0 Data Ready: This signal is asserted for each cycle that data is
transferred.
Processor 0 Differential Host Data Strobes: The differential source
synchronous strobes used to transfer FSB0D[63:0]# and FSB0DBI[3:0]# at
the 4X transfer rate.
Processor 0 Cache Hit: This signal indicates that a caching agent holds an
unmodified version of the requested line. FSB0HIT# is also driven in
conjunction with FSB0HITM# by the target to extend the snoop window.
Processor 0 Cache Hit Modified: This signal indicates that a caching agent
holds a modified version of the requested line and that this agent assumes
responsibility for providing the line. FSB0HITM# is also driven in conjunction
with FSB0HIT# to extend the snoop window.
Processor 0 Lock: This signal indicates to the system that a transaction
must occur atomically. This signal must connect the appropriate pins of all
processor FSB agents. For a locked sequence of transactions, LOCK# is
asserted from the beginning of the first transaction to the end of the last
transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the
processor FSB, it will wait until it observes LOCK# deasserted. This enables
symmetric agents to retain ownership of the processor FSB throughout the
bus locked operation and ensure the atomicity of lock.
Processor 0 Machine Check Error: Machine check error
Processor Bus 0 Request Command: These signals define the attributes
of the request. FSB0REQ[4:0]# are transferred at 2X rate. They are asserted
by the requesting agent during both halves of request phase. In the first half
the signals define the transaction type to a level of detail that is sufficient to
begin a snoop request. In the second half the signals carry additional
information to define the complete transaction type.
Processor 0 Reset: The FSB0RESET# pin is an output from the MCH. The
MCH asserts FSB0RESET# while RSTIN# (PCIRST# from Intel 631xESB/
632xESB I/O Controller Hub) is asserted and for approximately 1 ms after
RSTIN# is deasserted. The FSB0RESET# allows the processors to begin
execution in a known state.
Processor 0 Response Status Signals: These signals indicate the type of
response according to the following:
Processor 0 Response Status Parity:
Processor Bus 0 Target Ready: This signal indicates that the target of the
processor transaction is able to enter the data transfer phase.
Processor 0 Voltage Reference: Processor 0 voltage reference.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
StrobeData Bits
FSB0DSTBP3#, FSB0DSTBN3#FSB0D[63:48]#, FSB0DBI3#
FSB0DSTBP2#, FSB0DSTBN2#FSB0D[47:32]#, FSB0DBI2#
FSB0DSTBP1#, FSB0DSTBN1#FSB0D[31:16]#, FSB0DBI1#
FSB0DSTBP0#, FSB0DSTBN0#FSB0D[15:0]#, FSB0DBI0#
Encoding Response Type
000 Idle state
001 Retry response
010 Deferred response
011 Reserved (not driven by MCH)
100 Hard Failure (not driven by MCH)
101 No data response
110 Implicit Writeback
111 Normal data response
Description
Signal Description