NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 280

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

4.2.3
Table 4-2.
4.2.4
280
Expansion Card BIOS Area (C 0000h–D FFFFh)
This 128-KB ISA Expansion Card BIOS covers segments C and D. This region is further
divided into eight, 16-KB segments. Each segment can be assigned one of four read/
write states: read only, write only, read/write, or disabled. Typically, these blocks are
mapped through the MCH and are subtractively decoded to ISA space. Memory that is
disabled is not remapped.
Read and write transactions may be directed to different destinations with in the range
C 0000h to D FFFFh. Historically, these blocks were used to shadow ISA device BIOS
code. For the Intel 5000P Chipset, these regions are used to provide address space to
PCI devices requiring memory space below 1 MB. The range is divided into 8 sub-
ranges. These ranges are defined by Intel 5000P Chipset MCH.PAM registers. There is a
PAM register for each sub-range that defines the routing of reads and writes.
PAM Settings
The power-on default for these segments is mapped read/write to the ESI port (Intel®
631xESB/632xESB I/O Controller Hub). Software should not set cacheable memory
attributes for any of these ranges, unless both reads and writes are mapped to main
memory. Chipset functionality is not guaranteed if this region is cached in any mode
other than both reads and writes being mapped to main memory.
For locks to this region, the Intel 5000P Chipset will complete, but does not guarantee
the atomicity of locked access to this range when writes and reads are mapped to
separate destinations. If inbound accesses are expected, the C and D segments MUST
be programmed to send accesses to DRAM.
Lower System BIOS Area (E 0000h–E FFFFh)
This 64-KB area, from E 0000h to E FFFFh, is divided into four, 16-KB segments. Each
segment can be assigned independent read and write attributes through the Intel
5000P Chipset MCH.PAM registers. This area can be mapped either the ESI port (Intel
631xESB/632xESB I/O Controller Hub) or to main memory. Historically this area was
used for BIOS ROM. Memory segments that are disabled are not remapped elsewhere.
The power-on default for these segments is to map them to the ESI port (Intel
631xESB/632xESB I/O Controller Hub). Software should not set cacheable memory
attributes for any of these ranges unless both read and write transactions are mapped
to main memory. Chipset functionality is not guaranteed if this region is cached.
For locks to this region, the Intel 5000P Chipset will complete them, but does not
guarantee the atomicity of locked access to this range when writes and reads are
mapped to separate destinations. If inbound transactions are expected, the E segment
MUST be programmed to send these transactions to DRAM.
PAM [5:4]/1:0]
00
01
10
11
ESI
ESI
Main Memory
Main Memory
Write Destination
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
ESI
Main Memory
ESI
Main Memory
Read Destination
Mapped to ESI Port
Memory Write Protect
In-Line Shadowed
Mapped to main memory
Result
System Address Map