NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 282

no-image

NQ5000P S L9TN

Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet

Specifications of NQ5000P S L9TN

Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
4.3.4
282
allows accesses to this range only when the SMMEM# signal on the processor bus is
asserted with the request. If SMMEM# is deasserted, accesses to the SMM Range are
master aborted. If SMMEM# is asserted the access is routed to main memory. Intel
5000P Chipset uses the SMM enable and range registers to determine where to route
the access.
Extended SMRAM Space is different than the SMM space defined with in the VGA
address space, A 0000h - B FFFFh. This region is controlled by the Intel 5000P Chipset
registers Intel 5000P Chipset MCH.EXSMRC.TSEG_SZ and Intel 5000P Chipset
MCH.EXSMRTOP.ESMMTOP. The TSEG SMM space starts at ESMMTOP - TSEG_SZ and
ends at ESMMTOP. This region may be 512 KB, 1 MB, 2 MB, or 4 MB in size, depending
on the TSEG_SZ field. ESMMTOP is relocatable to accommodate software that wishes to
configure the TSEG SMM space before MMIO space is known. The ESMMTOP will default
to the same default value as Top Of Low Memory (TOLM), defined by the TOLM register.
Intel 5000P Chipset will not support a locked access that crosses an SMM boundary.
Firmware should not create data structures that span this boundary. SMM main
memory is protected from Inbound accesses.
In order to make cacheable SMM possible, the chipset must accept EWB’s and must
absorb IWB data regardless of the condition of the SMMEM# pin. The Intel 5000P
Chipset MCH will not set the error bit EXSMRAMC.E_SMERR in this case. Because of
this, care must be used when attempting to cache SMM space. The chipset/platform
cannot protect against processors who attempt to illegally access SMM space that is
modified in another processor’s cache. Any software that creates such a condition (for
example, by corrupting the page table) will jeopardize the protective properties of
SMM.
Memory Mapped Configuration (MMCFG) Region
There is one relocatable memory mapped configuration region in the Intel 5000P
Chipset MCH. The processor bus address defines the particular configuration register to
be accessed. This configuration mechanism is atomic.
The memory mapped configuration region is compatible with the PCI Express enhanced
configuration mechanism. The MMCFG region is a 256 MB window that maps to PCI
Express registers on both the Intel 5000P Chipset and the south bridge.
The location of this MMCFG window is defined by the Intel 5000P Chipset
MCH.HECBASE register. The HECBASE register could also be accessed through a fixed
location. The default value of Intel 5000P Chipset MCH.HECBASE maps this region such
that there will be no wasted memory that is lost behind it. The default value for the PCI
Express registers is the same as the default value of TOLM. If this range is moved, the
following recommendations will enable reclaiming the memory that is lost to MMCFG
accesses.
BIOS/software must ensure there are no outstanding configuration accesses or
memory accesses to the old and new MMCFG range addresses when relocating this
range.
1. MMCFG range is mapped to a legal location within the range between TOLM and
2. Put the region above 4GB Low/Medium Memory limit and not overlapping above
4GB. Since ranges must not overlap other legal ranges, it is safest to put this range
between TOLM and the lowest real MMIO range. (The current default is in these
ranges) OR
4 GB MMIO space.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
System Address Map

Related parts for NQ5000P S L9TN