NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 283

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

System Address Map
Note:
4.3.5
Table 4-3.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
An SMM program can address up to 4 GB of memory. SMM is similar to read-address
mode in that there are no privileges or address mapping. The Intel 5000P Chipset MCH
allows the relocation of HECBASE above 4 GB. However, SMM code cannot access
extended configuration space if HECBASE is relocated above 4 GB. This is a CPU
limitation. Page Size Extension (PSE) is supported in SMM but Page Address Extension
(PAE) support in SMM is currently not in Intel
Intel
For more information on the memory mapped configuration mechanism described here,
please see the Configuration Map and Access Chapter.
Low Memory Mapped I/O (MMIO)
This is the first of two Intel 5000P Chipset memory mapped I/O ranges. The low
memory mapped I/O range is defined to be between Top Of Low Memory, (TOLM) and
FE00 0000h. This low MMIO region is further subdivided between the PCI Express and
ESI ports. The following table shows the registers used to define the MMIO ranges for
each PCI Express/ESI device. These registers are compatible with PCI Express and the
PCI to PCI bridge specifications. Note that all subranges must be contained in the low
memory mapped I/O range (between TOLM and FE00 0000). In other words, the lowest
base address must be above TOLM and the highest LIMIT register must be below
FE00_0000. Subranges must also not overlap each other.
Low Memory Mapped I/O
Notes:
1.
2.
The Intel 5000P Chipset MCH will decode addresses in this range and route them to the
appropriate ESI or PCI Express port. If the address is in the low MMIO range, but is not
contained in any of the PCI Express base and limit ranges, it will be routed to the ESI.
If the Intel 5000P Chipset MCH.PMLU and Intel 5000P Chipset MCH.PMBU registers are
greater than 0, then the corresponding prefetchable region will be located in the high
MMIO range instead.
ESI
PEX2 Memory
PEX2 Prefetchable Memory
PEX3 Memory
PEX3 Prefetchable Memory
PEX4 Memory
PEX4 Prefetchable Memory
PEX5 Memory
PEX5 Prefetchable Memory
PEX6 Memory
PEX6 Prefetchable Memory
PEX7 Memory
PEX7 Prefetchable Memory
This table assumes Intel 5000P Chipset MCH.PMLU and Intel 5000P Chipset MCH.PMBU are 0’s. Otherwise,
the prefetchable memory space will be located in high MMIO space.
MCH does not need base/limit for Intel 631xESB/632xESB I/O Controller Hub because subtractive decoding
will send the accesses to the Intel 631xESB/632xESB I/O Controller Hub. This is OK for software also, since
the Intel 631xESB/632xESB I/O Controller Hub is considered part of the same bus as the MCH.
®
Architecture Software Developer’s Manual, Vol. 3, Sect. 13.1.
I/O Port
N/A
MBASE2
PMBASE2
MBASE3
PMBASE3
MBASE4
PMBASE4
MBASE5
PMBASE5
MBASE6
PMBASE6
MBASE7
PMBASE7
1
2
MCH Base
®
N/A
MLIMIT2
PMLIMIT2
MLIMIT3
PMLIMIT3
MLIMIT4
PMLIMIT4
MLIMIT5
PMLIMIT5
MLIMIT6
PMLIMIT6
MLIMIT7
PMLIMIT7
Xeon
2
MCH Limit
®
processors. Refer to the IA-32
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