NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 286

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

4.3.7.3
4.3.7.4
4.3.7.5
4.3.8
4.3.8.1
4.3.8.2
4.3.8.3
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that is modified in another processor’s cache. Any software that creates such a
condition (for example, by corrupting the page table) will jeopardize the protective
properties of SMM.
Interrupt Range
Requests to the address range FEE0 0000h to FEEF FFFFh are used to deliver
interrupts. Memory reads or write transactions to this range are illegal from the
processor. The processor issues interrupt transactions to this range. Inbound interrupt
requests from the PCI Express devices in the form of memory writes are converted by
the MCH to processor bus interrupt requests.
Reserved Ranges
The Intel 5000P Chipset MCH will master abort requests to the addresses in the
interrupt/reserved range (FEC0 0000h - FEFF FFFFh) which are not specified. This can
be done by sending the request to the compatibility bus (ESI) to be master aborted.
Firmware Range
The Intel 5000P Chipset platform allocates 16 MB of firmware space from FF00 0000h
to FFFF FFFFh. Requests in this range are directed to the Compatibility Bus. The Intel
631xESB/632xESB I/O Controller Hub will route these to its FWH interface. This range
is accessible from any processor bus.
High Extended Memory
This is the range above 4 GB. The range from 4 GB to Intel 5000P Chipset
MCH.MIR[2].LIMIT is mapped to system memory. There can also be a memory mapped
I/O region that is located at the top of the address space. (Just below 1 TB).
System Memory
See
High MMIO
The high memory mapped I/O region is located above the top of memory as defined by
Intel 5000P Chipset MCH.MIR[2].LIMIT. These Intel 5000P Chipset MCH.PMBU and Intel
5000P Chipset MCH.PMLU registers in each PCI Express configuration device determine
whether there is memory mapped I/O space above the top of memory. If an access is
above MIR[2].LIMIT and it falls within the Intel 5000P Chipset MCH.PMBU+PMBASE and
Intel 5000P Chipset MCH.PMLU+PMLIMIT range, it should be routed to the appropriate
PCI Express port. For accesses above MIR[2].LIMIT (and above 4 GB) that are not in a
high MMIO region, they should be master aborted.
Extended Memory
The range of memory just below 4 GB from TOLM to 4 GB (Low MMIO, Chipset,
Interrupt/SMM/LT) does not map to memory. If the DRAM memory, behind the TOLM to
4 GB range, is not relocated, it will be unused.
The Intel 5000P Chipset MCH uses MIR[2].LIMIT to indicate the top of usable memory.
Note that ESMMTOP cannot be greater than TOLM.
Section 4.3.9
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
System Address Map