NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 288

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Table 4-5.
4.4.2
Table 4-6.
288
Intel 5000P Chipset MCH Memory Mapping Registers (Sheet 2 of 2)
a. The chipset treats memory and prefetchable memory the same. These are just considered 2 apertures to the
Address Disposition for Processor
The following tables define the address disposition for the Intel 5000P Chipset MCH.
Table 4-6
MCH on the processor bus.
entering the Intel 5000P Chipset MCH on an I/O bus. For address dispositions of PCI
Express/ESI devices, please refer to the respective product specifications for the
Intel 6700PXH 64 bit PCI Hub or Intel 631xESB/632xESB I/O Controller Hub.
Address Disposition for Processor (Sheet 1 of 2)
Notes:
DOS
SMM/VGA
C and D BIOS
segments
PCI Express port.
PMLIMIT (dev 2-7)
PMBASE (dev 2-7)
PCICMD (dev 2-7)
Address
MLIMIT (dev 2-7)
Range
PMBU (dev 2-7)
PMLU (dev 2-7)
Name
defines the disposition of outbound requests entering the Intel 5000P Chipset
0 to 09FFFFh
0A0000h to 0BFFFFh
0C0000h to 0DFFFFh and PAM=11
Write to
0C0000h to 0DFFFFh and PAM=10
Read to
0C0000h to 0DFFFFh and PAM=01
Read to
0C0000h to 0DFFFFh and PAM=10
Write to
0C0000h to 0DFFFFh and PAM=01
0C0000h to 0DFFFFh and PAM=00
Limit address for memory mapped I/O to PCI Express ports 2 - 7.
Base address for memory mapped I/O to prefetchable memory of PCI Express
ports 2-7
Limit address for memory mapped I/O to prefetchable memory of PCI Express
ports 2-7.
Prefetchable Memory Base (Upper 32 bits) - Upper address bits to the base
address of prefetchable memory space. If the prefetchable memory is below 4 GB,
this register will be set to all 0’s.
Prefetchable Memory Limit (Upper 32 bits) - Upper address bits to the limit address
of prefetchable memory space. If the prefetchable memory is below 4 GB, this
register will be set to all 0’s.
MSE (Memory Space Enable) bit enables the memory and prefetchable ranges.
Conditions
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Table 4-10
a
defines the disposition of inbound requests
Coherent Request to Main Memory.
Route to main memory according to Intel 5000P
Chipset MCH.MIR registers. Apply Coherence Protocol.
see
Non-coherent request to main memory. Rout to
appropriate FB-DIMM device according to Intel 5000P
Chipset MCH.MIR registers.
Issue request to ESI.
Table 4-8
Function
Intel 5000P Chipset Behavior
and
Table
4-9.
System Address Map