NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 289

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

System Address Map
Table 4-6.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Address Disposition for Processor (Sheet 2 of 2)
E and F BIOS
segments
Low/Medium
Memory
Extended
SMRAM Space
Low MMIO
PCI Express
MMCFG
Intel 5000P
Chipset
specific
I/O APIC
registers
Intel®
631xESB/
632xESB I/O
Controller Hub
/ Intel®
631xESB/
632xESB I/O
Controller Hub
timers
High SMM
Interrupt
High Memory
High MMIO
All others
Firmware
Address
Range
0E0000h to 0FFFFFh and PAM=11
Write to
0E0000h to 0FFFFFh and PAM=10
Read to
0E0000h to 0FFFFFh and PAM=01
Read to
0E0000h to 0FFFFFh and PAM=10
Write to
0E0000h to 0FFFFFh and PAM=01
0E0000h to 0FFFFFh and PAM=00
10_0000 <= Addr < TOLM
ESMMTOP-TSEG_SZ <= Addr <
ESMMTOP
TOLM <= Addr < FE00_0000 and
falls into a legal BASE/LIMIT range
TOLM <= Addr < FE00_0000 and
not in a legal BASE/LIMIT range
HECBASE <= Addr <
HECBASE+256MB
FE00_0000h to FEBF_FFFFh AND
valid Intel 5000P Chipset memory
mapped register address plus AMB
targeted addresses
FE00_0000h to FEBF_FFFFh AND
(NOT a valid Intel 5000P Chipset
memory mapped register address
or NOT a valid AMB targeted
address)
FEC0_0000 to FEC8_FFFFh
FEC9_0000h to FED1_FFFF
FEDA_0000h to FEDB_FFFF
interrupt transaction to
FEE0_0000h to FEEF_FFFFh
(not really memory space)
memory transaction to
FEE0_0000h to FEEF_FFFFh
FF00_0000h to FFFF_FFFFh
1_0000_0000 to MIR[2].LIMIT
(max FF_FFFF_FFFF)
PMBU+PMBASE <= Addr <=
PMLU+PMLIMIT
All Others (subtractive decoding)
Conditions
Non-coherent request to main memory. Rout to
appropriate FB-DIMM device according to Intel 5000P
Chipset MCH.MIR registers.
Issue request to ESI.
Coherent request to main memory. Route to main
memory according to Intel 5000P Chipset MCH.MIR
registers. Coherence protocol is applied.
Note: The extended SMRAM space is within this range.
see
Request to PCI Express based on <MBASE/MLIMIT and
PMBASE/PMLIMIT> registers.
Send to ESI to be master aborted.
Convert to a configuration access and route according
to the Configuration Access Disposition.
Issue configuration access to memory mapped register
inside Intel 5000P Chipset or to the FB-DIMM based on
the context.
Send to ESI to be master aborted.
Non-coherent request to PCI Express or ESI based on
Table
Issue request to ESI.
see
Route to appropriate FSB(s).
Send to ESI to be master aborted.
Issue request to ESI.
Coherent request to main memory. Route to main
memory according to Intel 5000P Chipset MCH.MIR
registers. Coherence protocol is applied.
Route request to appropriate PCI Express port.
Issue request to ESI.
Table 4-8
Table 4-8
4-4.
Intel 5000P Chipset Behavior
and
and
Table
Table
4-9.
4-9.
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