NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 29

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Signal Description
2.1.2
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Processor Front Side Bus 1
FSB1A[35:3]#
FSB1ADS#
FSB1ADSTB[1:0]#
FSB1AP[1:0]#
FSB1BINIT#
FSB1BNR#
FSB1BPM[5:4]
FSB1BPRI#
FSB1BREQ[1:0]#
FSB1D[63:0]#
FSB1DBI[3:0]#
FSB1DBSY#
FSB1DEFER#
Signal Name
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
O
Type
Processor 1 Address Bus: FSB1A[35:3]# connect to the processor address
bus. During processor cycles, FSB1A[35:3]# are inputs. The MCH drives
FSB1A[35:3]# during snoop cycles on behalf of ESI and AGP/Secondary PCI
initiators. FSB1A[35:3]# are transferred at 2X rate. Note that the address is
inverted on the processor bus.
Note:
Processor 1 Address Strobe: The processor bus owner asserts FSB1ADS#
to indicate the first of two cycles of a request phase. The MCH can assert this
signal for snoop cycles and interrupt messages.
Processor 1 Address Strobe: FSB1ADSTB[1:0]# are source synchronous
strobes used to transfer FSB1A[35:3]# and FSB1REQ[4:0]# at the 2X
transfer rate.
Processor 1 Address Parity: FSB0AP[1:0]# provide parity protection on
the address bus
Processor 1 Bus Initialization: This signal causes a reset of the bus state
machines.
Processor 1 Block Next Request: This signal is used to block the current
request bus owner from issuing a new request. This signal is used to
dynamically control the processor bus pipeline depth.
Breakpoint /Debug Bus: These signals are breakpoint and performance
monitor signals. These are output from the processor to indicate the status
of breakpoints and programmable counters used for monitoring processor
performance.
Processor 1 Priority Agent Bus Request: The MCH is the only Priority
Agent on the processor bus. It asserts this signal to obtain ownership of the
address bus. This signal has priority over symmetric bus requests and cause
the current symmetric owner to stop issuing new transactions unless the
FSB1LOCK# signal was asserted.
Processor 1 Bus Requests: The MCH pulls the FSB1BREQ1# &
FSB1BREQ0# signals low during RESET#. The signal is sampled by the
processor on the active-to-inactive transition of FSB1RESET#. The minimum
setup time for this signal is 4 FSB1CLKs. The minimum hold time is 2 clocks
and the maximum hold time is 20 FSB1CLKs.
Processor 1 Data Bus: These signals are connected to the processor data
bus. Data on FSB1D[63:0]# is transferred at a 4X rate. Note that the data
signals may be inverted on the processor bus, depending on the
FSB1DBI[3:0] signals.
Processor 1 Dynamic Bus Inversion: These signals are driven along with
the FSB1D[63:0]# signals. They indicate if the associated signals are
inverted. FSB1DBI[3:0]# are asserted such that the number of data bits
driven electrically low (low voltage) within the corresponding 16-bit group
never exceeds 8.
Processor 1 Data Bus Busy: This signal is used by the data bus owner to
hold the data bus for transfers requiring more than one cycle.
Processor 1 Data Bus Defer: Defer indicates that the MCH will terminate
the transaction currently being snooped with either a deferred response or
with a retry response.
StrobeAddress Bits
FSB1ADSTB0#FSB1A[16:3]#, FSB1REQ[4:0]#
FSB1ADSTB1#FSB1A[35:17]#
FSB1DBI[x]#Data Bits
FSB1DBI3#FSB1D[63:48]#
FSB1DBI2#FSB1D[47:32]#
FSB1DBI1#FSB1D[31:16]#
FSB1DBI0#FSB1D[15:0]#
The MCH drives the FSB1A7# signal, which is then sampled by the
processor and the MCH on the active-to-inactive transition of
FSB1RESET#. The minimum setup time for this signal is 4
FSB0CLKs. The minimum hold time is 2 clocks and the maximum
hold time is 20 FSB1CLKs.
Description
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