NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 292

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Table 4-10. Address Disposition for Inbound Transactions (Sheet 1 of 2)
292
For all table entries where an access is forwarded to ESI to be master aborted, if an
access comes from ESI, the Intel 5000P Chipset MCHESI may master abort a
transaction without forwarding it back to the ESI.
BIOS segments
Low MMIO
PCI Express
MMCFG
Chipset specific
Intel 631xESB/
Controller Hub
Controller Hub
SMRAM Space
C, D, E, and F
632xESB I/O
632xESB I/O
Low/Medium
Intel 5000P
SMM/VGA
631xESB/
High SMM
Extended
Address
I/O APIC
Interrupt
registers
Firmware
Memory
Range
/ Intel
timers
DOS
0 to 09FFFFh
0A0000h to 0BFFFFh,
and VGAEN=0
0A0000h to 0BFFFFh
and VGAEN=1
0C0000h to 0FFFFFh and PAM=11
10_0000 <= Addr < ESMMTOP -
TSEG_SZ
ESMMTOP -TSEG_SZ <= Addr <
ESMMTOP
TOLM <= Addr < FE00_0000 and
falls into a legal BASE/LIMIT range
TOLM <= Addr < FE00_0000 and
not in a legal BASE/LIMIT range
HECBASE <= Addr <
HECBASE+256MB
FE00_0000h to FEBF_FFFFh AND
valid Intel 5000P Chipset memory
mapped register address
FE00_0000h to FEBF_FFFFh AND
NOT a valid Intel 5000P Chipset
memory mapped register address
FEC0_0000 to FEC8_FFFFh
FEC9_0000h to FED1_FFFF
FEDA_0000h to FEDB_FFFF
Inbound write to FEE0_0000h -
FEEF_FFFFh
memory transaction (other than
write) to FEE0_0000h -
FEEF_FFFFh
FF00_0000h to FFFF_FFFFh
Conditions
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
b
Coherent Request to Main Memory.
Route to main memory according to Intel 5000P
Chipset MCH.MIR registers. Apply Coherence Protocol.
Send to ESI to be master aborted. Set
EXSMRAMC.E_SMERR
Non-coherent read/write request to the decoded PCI
Express or to ESI based on BCTRL
Non-coherent request to main memory. (Coherency
does not need to be guaranteed. Coherency protocol
can be followed if it simplifies implementation.) Route
to appropriate FB-DIMM according to Intel 5000P
Chipset MCH.MIR registers.
Coherent Request to Main Memory. Route to main
memory according to Intel 5000P Chipset MCH.MIR
registers. Apply Coherence Protocol.
Send to system memory if G_SMRAME = 0 or
(G_SMRAME = 1 and T_EN = 0); otherwise Send to
ESI to be master aborted. Set EXSMRAMC.E_SMERR
bit
Request to PCI Express based on <MBASE/MLIMIT and
PMBASE/PMLIMIT> registers.
Send to ESI to be master aborted.
Inbound MMCFG access is not allowed and will be
aborted.
Inbound MMCFG access is not allowed and will be
aborted.
Send to ESI to be master aborted.
Non-coherent request to PCI Express or ESI based on
Table 4-4
Issue request to ESI.
Send to ESI to be master aborted. Set
EXSMRAMC.E_SMERR bit
Route to appropriate FSB(s). See Interrupt Chapter for
details on interrupt routing.
Send to ESI to be master aborted.
Master abort
Intel 5000P Chipset Behavior
System Address Map
a