NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 293

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

System Address Map
Table 4-10. Address Disposition for Inbound Transactions (Sheet 2 of 2)
4.5
4.5.1
4.5.2
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
a. One and only one BCTRL can set the VGAEN; otherwise, send to ESI for master abort.
b. Other combinations of PAM’s are not allowed if inbound accesses to this region can occur. Just like Cayuse,
I/O Address Map
The I/O address map is separate from the memory map and is primarily used to
support legacy code/drivers that use I/O mapped accesses rather than memory
mapped I/O accesses. Except for the special addresses listed in
accesses are decoded by range and sent to the appropriate ESI/PCI Express port, which
will route the I/O access to the appropriate device.
Special I/O Addresses
There are two classes of I/O addresses that are specifically decoded by the Intel 5000P
Chipset MCH:
Historically, the 64 K I/O space actually was 64 K+3 bytes. For the extra three bytes,
A#[16] is asserted on FSB. The Product Name decodes only A#[15:3] when the
request encoding indicates an I/O cycle. Therefore first three byte I/O accesses with
A#[16] asserted are decoded as if they were accesses to the first three bytes starting
from I/O addresses 0 (wrap-around the 64 KB line). A[16] is not forwarded by Intel
5000P Chipset MCH.
At power-on, all I/O accesses are mapped to the ESI.
Outbound I/O Access
The Intel 5000P Chipset MCH chipset allows I/O addresses to be mapped to resources
supported on the I/O buses underneath the Intel 5000P Chipset. This I/O space is
partitioned into 16 4 KB segments. Each of PCI Express port can have from 1 to 16
consecutive segments mapped to it by programming its IOBASE and IOLIM registers.
Each PCI Express port must be assigned contiguous segments. The lowest segment,
from 0 to 0FFFh, should be programmed to send to the ESI for compatibility.
Notes:
High Memory
High MMIO
All others
• I/O addresses used for VGA controllers.
• I/O addresses used for the PCI Configuration Space Enable (CSE) protocol. The I/O
chipset functionality is not guaranteed.
Address
addresses 0CF8h and 0CFCh are specifically decoded as part of the CSE protocol.
Range
1_0000_0000 to MIR[2].LIMIT
(max FF_FFFF_FFFF)
PMBU+PMBASE <= Addr <=
PMLU+PMLIMIT
All Others (subtractive decoding)
Conditions
Coherent Request to Main Memory. Route to main
memory according to Intel 5000P Chipset MCH.MIR
registers. Apply Coherence Protocol.
Route request to appropriate PCI Express port
Issue request to ESI.
Intel 5000P Chipset Behavior
Section
4.5.1, I/O
293