NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 301

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
Figure 5-1.
Figure 5-2.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Minimum Two DIMM Configuration
Figure 5-2
are depicted in dark gray. The two upgrade positions are Branch 0, Slot 1 and Branch 1,
Slot 0. Of these Branch 1, Slot 0 is the preferred upgrade because it allows both
branches to operate independently and simultaneously. FB-DIMM memory bandwidth is
doubled when both branches operate in parallel.
While it is possible to completely populate one branch before populating the second
branch, it is not desirable to do so from a performance standpoint. In general memory
upgrades should be balanced with respect to both branches to optimize FB-DIMM
performance.
Next Two DIMM Upgrade Positions
Figure 5-3
requires that the DIMM be placed in Branch 0, Channel 0, Slot 0. When upgrading from
this mode the normal two DIMM memory upgrade rules are followed.
SLOT 3
SLOT 2
SLOT 1
SLOT 0
SLOT 3
SLOT 2
SLOT 1
SLOT 0
depicts the next two positions where DIMMs may be added. These positions
depicts a special single DIMM non-mirrored operation mode. This mode
CHANNEL 0
CHANNEL 0
BRANCH 0
BRANCH 0
CHANNEL 1
CHANNEL 1
Memory Controller
Memory Controller
SLOT 3
SLOT 2
SLOT 1
SLOT 0
SLOT 3
SLOT 2
SLOT 1
SLOT 0
CHANNEL 2
CHANNEL 2
BRANCH 1
BRANCH 1
CHANNEL 3
CHANNEL 3
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