NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 310

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Figure 5-7.
Table 5-7.
310
The Intel 5000P Chipset MCH integrates a 100KHz SPD controller to access the DIMM
SPD EEPROM’s. There are four SPD ports. SPD0SMBDATA, and SPD0SMBCLK are
defined for channel 0; SPD1SMBDATA, and SPD1SMBCLK are defined for channel 1;
SPD2SMBDATA, and SPD2SMBCLK are defined for channel 2; and SPD3SMBDATA, and
SPD3SMBCLK are defined for channel 3. There can be a maximum of eight SPD
EEPROM’s associated with each SPD bus. Therefore, the SPD interface is wired as
indicated in
Connection of DIMM Serial I/O Signals
Board layout must map chip selects to SPD Slave Addresses as shown in
slave address is written to the SPDCMD configuration register (see
SPD Addressing
S L O T 3
S L O T 2
S L O T 1
S L O T 0
SPD Bus
0
1
2
3
S A 0
S A 1
S A 2
S A 0
S A 1
S A 2
S A 0
S A 1
S A 2
S A 0
S A 1
S A 2
Figure
C H A N N E L
FB-DIMM
Channel
5-7.
D IM M
D IM M
D IM M
D IM M
0
0
1
2
3
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
SLOT
C H A N N E L
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
D IM M
D IM M
D IM M
D IM M
1
Slave Address
S C L 0 /
S D A 0
S C L 1 /
S D A 1
In t e l® 5 0 0 0 P
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
S A 0
S A 1
S A 2
S A 0
S A 1
S A 2
S A 0
S A 1
S A 2
S A 0
S A 1
S A 2
C h ip s e t
S A 0
S A 1
S A 2
S A 0
S A 1
S A 2
S A 0
S A 1
S A 2
S A 0
S A 1
S A 2
S C L 3 /
S D A 2
S C L 2 /
S D A 3
C H A N N E L
D IM M
D IM M
D IM M
D IM M
2
Functional Description
Section
C H A N N E L
D IM M
D IM M
D IM M
D IM M
Table
3
3.9.26.2).
5-7. The
S A 0
S A 1
S A 2
S A 0
S A 1
S A 2
S A 0
S A 1
S A 2
S A 0
S A 1
S A 2