NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 315

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.2.10.5
5.2.11
5.2.11.1
5.2.11.2
5.2.11.3
5.2.11.4
5.2.11.5
5.2.12
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
ECC Code Layout for a Single-Channel Branch
The ninth byte of each burst on each DIMM contains the ECC bits for 8 bytes of data.
These nine bytes comprise a code word. There are eight code words in a cache line.
DDR2 Protocol
Posted CAS
Posted CAS timing is used.
Refresh
Regardless of the number of DIMMs installed, each rank will get a minimum of one
refresh every eight periods defined by the DRT.TREF configuration register field. The
refreshes cycle through all eight DIMM ranks.
The DIMM enters self-refresh mode during an FB-DIMM fast reset.
Access Size
All memory accesses are 64 B.
Transfer Mode
Each DIMM is programmed to use a burst-length of 32 bytes (4 transfers) across the
channel. The Mode Register of each DIMM must be programmed for a burst length of 4,
and interleave mode.
Invalid and Unsupported DDR Transactions
The memory controller prevents cycle combinations leading to data interruption or
early termination. The memory controller prevents combinations of DDR commands
that create bus contention (that is, where multiple ranks would be required to drive
data simultaneously on a DIMM). The memory controller does not interrupt writes for
reads. A precharge command is provided, but early read or write termination due to
precharge is not supported.
Memory Thermal Management
The Intel 5000P Chipset MCH supports FB-DIMM throttling and power management
through several mechanisms. The first mechanism forces power down of unused or
failed channels by setting the FB-DIMMHPC.State to Reset. This corresponds to the
Disable state in the FB-DIMM specification which holds the FB-DIMM channel in reset.
When in reset, the channel receivers and drivers are disabled.
The second method of power management utilizes an adaptive methodology to control
the number of activations (memory requests) sent to a FB-DIMM. This methodology is
composed of two components:
1. Activation throttling: This is composed of closed and open loop throttling
mechanisms to control the number of activations sent to FB-DIMM devices.
a. Closed loop thermal activation control is based on the temperature of the FB-
DIMM device. This mechanism becomes active when the FB-DIMM device
temperature exceeds programmed thresholds.
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