NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 317

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.2.12.2
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
1. The worst case round trip delay is expected to be in the 10-20 clock range for a posted CAS
command and the
The TEMPLO threshold is generally used to inform the host to accelerate refresh events.
The TEMPMID threshold is generally used to inform the host that a thermal limit has
been exceeded and that thermal throttling is needed.
There are separate counters associated with each of the 2 lockstep FB-DIMM pairs in a
given branch (one counter per FB-DIMM pair per branch). When any of the counters
reaches its limit (as specified by the THRTSTS.THRMTHRT register field for a given
branch), the entire branch is throttled until the end of the throttle window. No new
DRAM commands are issued to any of the DIMMs on the branch until the end of the
throttle window. If an activate has been issued to a bank, the follow on read or write
may be issued, including an additional page hit access if applicable, to allow the page
to close.
Sequence of Actions During Throttling
When throttling begins during a given throttling window, the following actions take
place:
Once the branch has been throttled, the memory controller sends a broadcast CKE for
each DIMM command to take the CKE low on all DIMMs of the branch. This command is
sent after the proper time has elapsed so that the outstanding transfers complete
properly on the DRAMs. When activation throttling starts, CKE must not go low on the
DRAMs until the last command has completed in the DRAMs. The worst case is an
activate immediately followed by a posted CAS. A fixed time from the last command is
used by the Intel 5000P Chipset MCH corresponding to the worst case delay (X) defined
by
with a suitable guard band
Activate Command delay) is factored into the equation since a refresh could be just
underway when the last activate was about to be issued. The “1.25” scaling factor is to
account for the 5:4 gearing ratio required for a FSB frequency of (333 MHz) and FBD/
DDR clock frequency of (266MHz). The default scale factor used on Intel 5000P Chipset
Intel® 5000X chipset platforms is 1 (FSB (266 MHz) and FBD/DDR clocks (266 MHz)).
During the time that CKE is low, no DRAM commands should be sent on the channel.
However, Non-DRAM commands such as Configuration register and SYNC are required
to be sent during this period.
When the throttle window is about to expire, a CKE command is sent to take all CKEs
high. This must be done at least 3 clocks before the first command.
1. Stop new DRAM commands
2. Wait “X” clocks for DRAM commands to complete. Where “X” is the worst case
3. Assert CKE low
4. Wait for throttling window to expire
5. Just before end of activation throttle window (about 3 clocks before for the CKE
delay as defined below
setup), Assert CKE high
Intel 5000P Chipset
X
=
M
Max worst_case_round_trip_delay M
=
1
⎧
⎨
⎩
to protect any data loss. The TRFC parameter (Refresh to
(
1.25 if Core to FBD clock ratio is 5:4
1 Otherwise
MCH RTL can be microarchitected appropriately.
,
¥
TRFC
)
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