NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 322

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Table 5-9.
5.2.12.7
322
1. If MC.GTW_MODE=1, the Intel 5000P Chipset MCH will use the 4*1344 cycle duration for the
global throttling window.
THRMTHRT
Reg Value
FB_DIMM Bandwidth as a Function of Closed Loop Thermal Throttling
Open Loop Global Throttling
In the open loop global window throttling scheme, the number of activates per DIMM
pair per branch is counted for a larger time period called the “Global Throttling
window”. The Global throttling window is chosen as an integral multiple of the thermal
throttling window of 1344 clocks for maintaining a simpler implementation. Under
normal operating conditions, the Global Throttling Window is 0.65625*2
duration and this translates to 16384*1344 clocks (~66.06 ms) for DDR2667. However,
for purposes of validation and debug, the global throttling window can be reduced to a
smaller duration, 4*1344 cycles
through the GTW_MODE register bit defined in
window prevents shorts peaks in bandwidth from causing closed loop activation
throttling when there has not been sufficient DRAM activity over a long period of time
to warrant throttling. It is in effect a low pass filter on the closed loop activation
throttling.
128
144
160
168
12
16
20
24
28
32
36
40
44
48
64
72
80
96
0 unlimited
1
2
3
4
5
6
7
8
Activates
112
128
144
160
176
192
256
288
320
384
512
576
640
672
12
16
20
24
28
32
48
64
80
96
4
8
allowed
% BW
100.00%
11.90%
14.29%
16.67%
19.05%
21.43%
23.81%
26.19%
28.57%
38.10%
42.86%
47.62%
57.14%
76.19%
85.71%
95.24%
0.60%
1.19%
1.79%
2.38%
2.98%
3.57%
4.17%
4.76%
7.14%
9.52%
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
1
DIMM GB/s
(16.128 μs) for DDR2667 and this is controlled
BW per
0.03
0.06
0.10
0.13
0.16
0.19
0.22
0.25
0.38
0.51
0.63
0.76
0.89
1.02
1.14
1.27
1.40
1.52
2.03
2.29
2.54
3.05
4.06
4.57
5.08
5.33
sys BW, 1
DIMM/ch
Section 3.9.1.
10.16
12.19
16.25
18.29
20.32
21.33
0.13
0.25
0.38
0.51
0.63
0.76
0.89
1.02
1.52
2.03
2.54
3.05
3.56
4.06
4.57
5.08
5.59
6.10
8.13
9.14
sys BW 2
DIMM/ch
The global throttling
10.16
11.17
12.19
16.25
18.29
20.32
0.25
0.51
0.76
1.02
1.27
1.52
1.78
2.03
3.05
4.06
5.08
6.10
7.11
8.13
9.14
Functional Description
sys BW 4
DIMM/ch
25
clocks in
10.16
12.19
14.22
16.25
18.29
20.32
0.51
1.02
1.52
2.03
2.54
3.05
3.56
4.06
6.10
8.13