NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 323

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.2.12.8
Note:
5.2.12.9
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
1. The 2 window Global Throttling count will be chosen if MC.GTW_MODE=1.
During this Global throttling window, the number of activates is counted for each DIMM
pair per branch (24-bit counters are required). If the number exceeds the number
indicated by the GBLACT.GBLACTLM register defined in
THRTSTS[1:0].GBLTHRT bit is set for the respective branch, causing the activation
throttling logic to use the THRTMID register. The THRTSTS[1:0].GBLTHRT will remain
active until 16 (or 2) global throttling windows in a row have gone by without any DIMM
exceeding the GBLACT.
At the end of the 16 (or 2) global throttling windows, if no DIMM pair activates exceed
the GBLACT.GBLACTLM value, then the MC indicates the end of the period by clearing
the THRTSTS[1:0].GBLTHRT register field.
If part way through the count of 16 (or 2) global throttling windows, the
GBLACT.GBLACTLM is again exceeded within one Global Throttle Window, the counter
gets reset and it will once again count 16 (or 2) global throttle windows throttling at the
THRTMID level.
Global Activation Throttling Software Usage
In practice, the throttle settings for THRTMID are likely to be set by software such that
the memory controller throttle logic will actually prevent the GBLACT limit from being
exceeded and the result will often be that such that THRTLOW is used for a Global
Throttle Window, at which time, the GBLACT.GBLACTLM is exceeded, causing the MC s
to use a larger throttling period THRTMID for 16 (or 2) global
those global windows, GBLACT limit is not exceeded, because the throttling will prevent
it from being exceeded. After 16 (or 2) global
THRTLOW, and on the next global window GBLACT is again exceeded, causing another
16 (or 2) windows
global
DIMMs by prolonging the throttle period.
It should be mentioned that the open and closed loop throttling control policies
implemented on the Intel 5000P Chipset MCH uses the internal core clocks for the
calculating the windows and not the DDR clocks. Thus any software/BIOS should take
this into account for manipulating the THRMTHRT registers when dealing with different
FB-DIMM technologies and speeds.
Dynamic Update of Thermal Throttling Registers
In general, the Intel 5000P Chipset registers should not updated dynamically during
runtime as it may interfere with the internal state machines not designed exclusively
for such changes and could result in a system hang/lock up. This requirement is
relaxed (subject to validation) for the Intel 5000P Chipset thermal throttling registers
where it is desirable for BIOS or special OEM software in BMC to exercise dynamic
control on throttling for open/closed loop algorithm implementation. The following
examples are some of the potential areas of this usage model where dynamic change is
needed to balance performance and acoustic levels in the system
Fan control for CPU temperature related system acoustics or other BMC related
operations. Limit hacker activity by increasing memory throttling via throttle register
updates to condition the system based on some event (excessive bandwidth or CPU
activity)
• Fan failure/breakdown. When this occurs, temperature conditioning can be
provided by reducing the activity level in the DIMMs to a certain threshold until the
failed fan can be repaired by the technician and service restored to normalcy.
2
throttling windows and this prevents excessive heat dissipation in the FB-
2
. Hence, we can get a cumulative pattern of 16,1,16,1 (or 2,1,2,1)
2
throttling windows, it switches back to
Section
1
windows. During each of
3.9.2, then the
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