NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 328

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Figure 5-13. XAPIC Address Encoding
Table 5-12. XAPIC Data Encoding
5.5.2
5.5.2.1
328
both the PCI Express bus and processor bus. Note that the current assumption is that
we can’t make any conclusions about which FSB an interrupt ID is associated with. At
power-up, there is an association for certain types of interrupts, but the current
assumption is that the OS can reprogram the interrupt ID’s. Therefore, for directed
interrupts, the Intel 5000P Chipset MCH will ensure that each interrupt is seen on both
FSBs.
The data fields of an interrupt transaction are defined by the processor and XAPIC
specifications. It is included here for reference.
XAPIC Destination Modes
The destination mode refers to how the processor interprets the destination field of the
interrupt message. There are two types of destination modes; physical destination
mode, and logical destination mode. The destination mode is selected by A[2] in PCI
Express and Ab[5] on the processor bus.
Physical Destination Mode (XAPIC)
In physical mode, the APIC ID is 8 bits, supporting up to 255 agents. Each processor
has a Local APIC ID Register where the lower 5 bits are initialized by hardware (Cluster
ID=ID[4:3], Bus Agent ID=ID[2:1], thread ID=ID[0]). The upper 3 bits default to 0’s
at system reset. These values can be modified by software. The Cluster ID is set by
address bits A[12:11] during reset. By default, the Intel 5000P Chipset will drive
A[12:11] to ‘00 for FSB0, and ‘01 for FSB1. The value driven on bit A[12] during reset
can be modified through the POC register on the Intel 5000P Chipset MCH.
The Intel 5000P Chipset will not rely on the cluster ID or any other fields in the APIC ID
to route interrupts. The Intel 5000P Chipset will ensure the interrupt is seen on both
busses and the processor with the matching APIC ID will claim the interrupt.
Physical destination mode interrupts can be directed, broadcast, or redirected. An
XAPIC message with a destination field of all 1’s denotes a broadcast to all.
In a directed physical mode message the agent claims the interrupt if the upper 8 bits
of the destination field (DID field) matches the Local APIC ID of the processor or the
interrupt is a broadcast interrupt.
Redirected interrupts are redirected and converted to a directed interrupt by the
chipset as described in
D[63:16]
DID: 8-bit destination ID. Software may assign each ID to any value
EDID: Not used, is a reserved field in the Processor EHS.
rh: redirection bit (0=directed, 1=redirectable)
dm: destination mode (0=physical, 1=logical)
*: PCI/PCI Express transaction encoding. Copied to Ab5 on processor bus
31
x
0xFEE
Trigger Mode
D[15]
Section 5.5.3.2.
20 19
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Delivery Status
DID
D[14]
12 11
D[13:11]
EDID (not used)
x
Delivery Mode
D[10:8]
.
4
rh dm rsvd
Functional Description
3
2*
D[7:0]
Vector
0