NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 329

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.5.2.2
5.5.2.3
Table 5-13. Intel 5000P Chipset XAPIC Interrupt Message Routing and Delivery
5.5.3
5.5.3.1
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Logical Destination Mode (XAPIC)
In logical destination mode, destinations are specified using an 8 bit logical ID field.
Each processor contains a register called the Logical Destination Register (LDR) that
holds this 8-bit logical ID. Interpretation of the LDR is determined by the contents of
the processor’s Destination Format Register (DFR). Processors used with the Intel
5000P Chipset MCH operate in flat mode. Logical destination mode interrupts can be
directed (fixed delivery), redirectable (lowest priority delivery), or broadcast. The LDR
is initialized to flat mode (0) at reset and is programmed by firmware. The Intel 5000P
Chipset also has an equivalent bit in the External Task Priority Register (XTPR0) to
indicate flat or cluster mode. This is set to flat mode by reset and must not be changed,
since the processors used with Intel 5000P Chipset operate in flat mode only.
The 8-bit logical ID is compared to the 8-bit destination field of the incoming interrupt
message. If there is a bit-wise match, then the local XAPIC is selected as a destination
of the interrupt. Each bit position in the destination field corresponds to an individual
Local XAPIC Unit. The flat model supports up to 8 agents in the system. An XAPIC
message where the DID (destination field) is all 1’s is a broadcast interrupt.
XAPIC Interrupt Routing
Interrupt messages that originate from I/O(x)APIC devices or from processing nodes
must be routed and delivered to the target agents in the system. In general XAPIC
messages are delivered to both processor busses because there is no reliable way to
determine the destination processor of the message from the destination field.
Interrupts originating from I/O can be generated from a PCI agent using MSI
interrupts, or by an interrupt controller on a bridge chip such as the Intel 631xESB/
632xESB I/O Controller Hub. Table 5-13 shows the routing rules used for routing
XAPIC messages in a Intel 5000P Chipset-based platform. This table is valid for both
broadcast and non-broadcast interrupts.
Interrupt Redirection
The XAPIC architecture provides for lowest priority delivery through interrupt
redirection by the Intel 5000P Chipset. If the redirectable “hint bit” is set in the XAPIC
message, the chipset may redirect the interrupt to another agent. Redirection of
interrupts can be applied to both I/O interrupts and IPIs.
XTPR Registers
To accomplish redirection, the Intel 5000P Chipset MCH implements a set of External
Task Priority registers (XTPRs), one for each logical processor (a thread is considered a
logical processor). Each register contains the following fields:
I/O
Processor
Any Source
1. Agent priority (Task Priority)
2. APIC enable bit (TPR Enable)
Source
physical or logical directed
physical or logical directed
logical, redirectable
physical, redirectable
Type
Deliver to all processor busses as an interrupt
transaction.
Deliver to other processor bus as an interrupt
transaction.
Redirection (see “Interrupt Redirection” on
page 352) is performed by the Intel 5000P
Chipset MCH and is delivered to both FSBs.
Routing
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