NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 333

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.7
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
For interrupts that are not coming through an APIC controller, it is still required that the
interrupt appear as an MSI-like interrupt. If the OS does not yet support MSI, the PCI
Express device can be programmed by the BIOS to issue inbound MSI interrupts to an
IOxAPIC in the system. The safest IOxAPIC to choose would be the Intel 631xESB/
632xESB I/O Controller Hub since it is always present in a system. Although the Intel
5000P Chipset supports the PCI Express “Assert_Int” and “Deassert_Int” packets for
boot, the performance is not optimal and is not recommended for run time interrupts.
In this method, PCI Express devices are programmed to enable MSI functionality, and
given a write path directly to the pin assertion register in a selected IOxAPIC already
present in the platform. The IOxAPIC will generate an interrupt message in response,
thus providing equivalent functionality to a virtual (edge-triggered) wire between the
PCI Express endpoint and the I/OxAPIC. This mechanism is the same as is used in
Longhorn* (XYZZY).
All PCI Express devices are strictly required to support MSI. When MSI is enabled, PCI
Express devices generate a memory transaction with an address equal to the I/
OxAPIC_MEM_BAR + 20 and a 32-bit data equal to the interrupt vector number
corresponding to the device. This information is stored in the device's MSI address and
data registers, and would be initialized by the system firmware (BIOS) prior to booting
a non-MSI aware operating system. (With the theory that an MSI aware O/S would
then over-write the registers to provide interrupt message delivery directly from the
endpoint to the CPU complex.)
The PCI Express memory write transaction propagates to the Intel 5000P Chipset and
is redirected down the appropriate PCI Express port following the Intel 5000P Chipset
IOAPIC address mapping definition. The IOAPIC memory space ranges are fixed and
cannot be relocated by the OS. The assert message is indistinguishable from a memory
write transaction, and is forwarded to the destination I/OxAPIC, which will then create
an upstream APIC interrupt message in the form of an inbound memory write. The
write nature of the message “pushes” all applicable pre-interrupt traffic through to the
Intel 5000P Chipset core, and the Intel 5000P Chipset core architecture guarantees
that the subsequent APIC message cannot pass any posted data already within the
Intel 5000P Chipset.
Interprocessor Interrupts (IPIs)
• Previous IA-32 processors use IPIs after reset to select the boot strap processor
• IA32 processors use Startup IPIs (SIPIs) to wake up sleeping application
• Interrupts transactions are claimed with TRDY# and No-Data Response.
• For directed XAPIC (A[3] = 0) interrupts, the Intel 5000P Chipset completes the
• For redirectable XAPIC interrupts, the Intel 5000P Chipset will generate an
• For directed XAPIC broadcast interrupts (Destination ID = 0xFF), the Intel 5000P
• Interrupts are not deferred.
(BSP). Recent XPF processors do not use IPIs to select the BSP. A hardware
arbitration mechanism is used instead.
processors (non boot strap processors) that are in “Wait for SIPI state”. These are
broadcast interrupts.
interrupt normally and forwards the interrupt to the other bus.
interrupt message to both processor buses Intel 5000P Chipset with A[3]
(redirectable hint bit) set to 0. This message will contain a processor ID based on
the redirection algorithm.
Chipset will forward the broadcast interrupt to the other processor bus.
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