NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 339

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.9
5.10
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Legacy/8259 Interrupts
8259 interrupt controller is supported in Intel 5000P Chipset platforms. 8259 interrupt
request is delivered using the interrupt group sideband signals LINT[1:0] (a.k.a. NMI/
INTR) or through an I/O xAPIC using the message based interrupt delivery mechanism
with the delivery mode set to ExtINT (111b). There can be only one active 8259
controller in the system.
The mechanism in which a PCI Express device requests an 8259 interrupt is a PCI
Express inband message. (ASSERT_INTA/B/C/D, DEASSERT_INTA/B/C/D).
The target processor for the interrupt uses the interrupt acknowledge transaction to
obtain the interrupt vector from the 8259 controller. The Intel 5000P Chipset forwards
the interrupt acknowledge to the Intel® 631xESB/632xESB I/O Controller Hub where
the active 8259 controller resides.
The Intel 5000P Chipset will support PCI Express devices that generate 8259 interrupts
(for example, during boot). 8259 interrupts from PCI Express devices will be sent in-
band to the Intel 5000P Chipset which will forward these interrupts to the Intel
631xESB/632xESB I/O Controller Hub.
The Intel 5000P Chipset will have a mechanism to track inband 8259 interrupts from
each PCI Express and assert virtual interrupt signals to the 8259 through the inband
“Assert_(Deassert)_Intx” messages. This is done by a tracking bit per interrupt (A, B,
C, D) in each PCI Express which are combined (OR’d) into virtual signals that are sent
to the Intel® 631xESB/632xESB I/O Controller Hub. Each interrupt signal (A, B, C, D)
from each PCI Express is OR’ed together to form virtual INT A, B, C, and D signals to
the Intel® 631xESB/632xESB I/O Controller Hub (Assert_(Deassert)_IntA/B/C/D
(assertion encoding)). When all of the tracking bits for a given interrupt (A, B, C, or D)
are cleared from all PCI Express ports, the virtual signal A, B, C, or D is deasserted via
the inband Deassert_Intx message.
For PCI Express hierarchies, interrupts will be consolidated at each level. For example,
a PCI Express switch connected to a Intel 5000P Chipset PCI Express port will only send
a maximum of 4 interrupts at a time, regardless of how many interrupts are issued
downstream.
SMI (System Management Interrupt) interrupts are initiated by the SMI# signal in the
platform. On accepting a System Management Interrupt, the processor saves the
current state and enters SMM mode.
Note that the Intel 5000P Chipset core components do not interact with the LINT[1:0]
and SMI signals. They are present on the Intel 631xESB/632xESB I/O Controller Hub
and the processor. Intel 5000P Chipset interrupt signals described in
routed to the Intel 631xESB/632xESB I/O Controller Hub to generate an SMI interrupt.
Similarly SCI interrupts can be generated by routing Intel 5000P Chipset interrupt
signals to the appropriate Intel® 631xESB/632xESB I/O Controller Hub pin.
Interrupt Error Handling
Software must configure the system so that each interrupt has a valid recipient. In the
event that an interrupt doesn’t have a valid recipient, since the Intel 5000P Chipset will
not necessarily know that the interrupt is targeted for a non-existing processor, will
deliver the interrupt to the processor buses following the interrupt routing rules
described in this chapter. If the interrupt targets a non-existing processor, it may be
ignored but the transaction should still complete.
Section 5.8
can be
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