NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 344

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NQ5000P S L9TN

Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet

Specifications of NQ5000P S L9TN

Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
5.12.2
5.12.3
Figure 5-17. ESI and PCI Express Ports 2 and 3
344
Enterprise South Bridge Interface (ESI)
The ESI is the Intel 631xESB/632xESB I/O Controller Hub to Intel 5000P Chipset MCH
interface. The available bandwidth to the Intel 631xESB/632xESB I/O Controller Hub
can be increased by using the one or more of the PCI Express ports 2 and 3.
Figure 5-17
PCI Express Ports 2 and 3
The PCI Express ports 2 and 3 are general purpose x4 PCI Express ports that may be
used to connect to PCI Express devices. The possible configurations of the PCI Express
ports are depicted in
Intel 631xESB/632xESB I/O Controller Hub, bandwidth is definable from 1GB/s in each
direction up to a maximum of 6 GB/s bi-directional.
combinations of ESI and ports 2 and 3 connecting to the Intel 631xESB/632xESB I/O
Controller Hub. Ports 2 and 3 are also general purpose PCI Express ports that may be
used as high performance interfaces to other PCI Express devices.
depicts the ESI port and PCI Express ports 2 and 3.
Figure
I n t e l ®
C o n t r o l l e r H u b
P o r t 0
T r a n s a c t i o n
D M I
T r a n s a c t i o n
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
5-17. By configuring ports 2 and 3 with the ESI port to the
P h y s i c a l
P h y s i c a l
6 3 1 x E S B / 6 3 2 x E S B
M C H
L i n k
L i n k
I / O
Figure 5-18
depicts the various
Functional Description

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