NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 35

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Signal Description
2.4
2.5
2.6
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
System Management Bus Interfaces
There are seven SM Bus interfaces dedicated to specific functions. These functions are:
XD Port Signal List
JTAG Bus Signal List
CFGSMBCLK
CFGSMBDATA
GPIOSMBCLK
GPIOSMBDATA
SPD0SMBCLK
SPD0SMBDATA
SPD1SMBCLK
SPD1SMBDATA
SPD2SMBCLK
SPD2SMBDATA
SPD3SMBCLK
SPD3SMBDATA
XDPCOMCRES
XDPD[15:0]#
XDPSTBN#
XDPSTBP#
XDPODTCRES
XDPRDY#
XDPSLWCRES
TCK
TDI
TDO
TMS
TRST#
• System Management
• Four buses dedicated to FB-DIMM serial presents detect, one for each channel
• PCI hot-plug
Signal Name
Signal Name
Signal Name
Analog
Analog
Analog
Type
Type
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
I
I
Slave SMB Clock: System Management Bus Clock
Slave SMB Data: SMB Address/Data
PCI SMB Clock: PCI Hot-Plug Master VPI, System Management Bus Clock
PCI SMB Data: PCI Hot-Plug Master VPI, SMB Address/Data
FB-DIMM Channel 0 SMB Clock: FB-DIMM Memory Serial Presents Detect 0,
System Management Bus Clock
FB-DIMM Channel 0 SMB Data: FB-DIMM Memory Serial Presents Detect 0,
SMB Address/Data
FB-DIMM Channel 1 SMB Clock: FB-DIMM Memory Serial Presents Detect 1,
System Management Bus Clock
FB-DIMM Channel 1 SMB Data: FB-DIMM Memory Serial Presents Detect 1,
SMB Address/Data
FB-DIMM Channel 2 SMB Clock: FB-DIMM Memory Serial Presents Detect 2,
System Management Bus Clock
FB-DIMM Channel 2 SMB Data: FB-DIMM Memory Serial Presents Detect 2,
SMB Address/Data
FB-DIMM Channel 3 SMB Clock: FB-DIMM Memory Serial Presents Detect 3,
System Management Bus Clock
FB-DIMM Channel 3 SMB Data: FB-DIMM Memory Serial Presents Detect 3,
SMB Address/Data
XDP Bus Compensation:
Data Bus:.
Data Bus Strobe Negative and Positive Phases:
XDP Bus Compensation:
Data Bus Ready:
XDP Bus Slew Rate Compensation:.
Clock: Clock pin of the JTAG.
Data Input: Serial chain input of the JTAG.
Data Output: Serial chain output of the JTAG.
State Machine: JTAG State machine control
Reset: Asynchronous reset of the JTAG.
Description
Description
Description
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