NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 354

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NQ5000P S L9TN

Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet

Specifications of NQ5000P S L9TN

Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
5.12.9.1
5.12.10
Figure 5-24. PCI Express Packet Visibility By Transaction Layer
5.13
5.13.1
354
Credit Update Mechanism, Flow Control Protocol (FCP)
After reset, credit information is initialized with the values indicated in
following the flow control initialization protocol defined in the PCI Express Base
Specification, Revision 1.0a. Since the MCH supports only VC0, only this channel is
initialized.
Transaction Layer
The PCI Express Transaction Layer is responsible for sending read and write operations
between components. This is the PCI Express layer which actually moves software
visible data between components. The transaction layer provides the mechanisms for:
Figure 5-17
Some transaction layer packets have only a header (for example, read request). Some
transaction layer packets have a header followed by data (for example, write requests
and read completions).
Power Management
The Intel 5000P Chipset MCH power management support includes:
Supported ACPI States
The MCH supports the following ACPI States:
• Software configuration of components
• Communication between the processor bus and different I/O technologies
• Communication between the memory and different I/O technologies
• ACPI supported
• System States: S0, S1 (desktop), S3, S4, S5, C0, C1, C2 (desktop)
• Processor
• System
— C0: Full On.
— C1: Auto Halt.
— C2 Desktop: Stop Grant. Clock to processor still running. Clock stopped to
— G0/S0: Full On.
— G1/S1: Stop Grant, Desktop S1, same as C2.
— G1/S2: Not supported.
— G1/S3: Suspend to RAM (STR). Power and context lost to chipset.
— G1/S4: Suspend to Disk (STD). All power lost (except wake-up logic on Intel®
processor core.
631xESB/632xESB I/O Controller Hub).
illustrates the scope of the transaction layer on a PCI Express packet.
Hdr
Hdr
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Payload
Functional Description
Table 5-16
by

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