NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 355

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.13.2
5.13.3
5.14
5.14.1
Figure 5-25. Intel 5000P Chipset Power Sequencing
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
FB-DIMM Thermal Management
The Intel 5000P Chipset MCH implements the following thermal management
mechanisms. These mechanisms manage the read and write cycles of the system
memory interface to implement thermal throttling.
Hardware-Based Thermal Management
The number of hex-words transferred over the DRAM interface are tracked per row. The
tracking mechanism takes into account that the DRAM devices consume different levels
of power based on cycle type (page hit/miss/empty). If the programmed threshold is
exceeded during a monitoring window, the activity on the DRAM interface is reduced.
This helps in lowering the power and temperature.
Software-Based Thermal Management
This is used when the external thermal sensor in the system interrupts the processor to
engage a software routine for thermal management.
FB-DIMM Thermal Diode Overview
The FB-DIMM Advanced Memory Buffer (AMB) contains an internal thermal diode to
measure AMB / DIMM temperature. Upon detecting a thermal over temperature
condition the AMB initiates a thermal throttling event. For more information see the
Gold Bridge Component External Design Specification.
System Reset
The Intel 5000P Chipset MCH is the root of the I/O subsystem tree, and is therefore
responsible for general propagation of system reset throughout the platform. The MCH
must also facilitate any specialized synchronization of reset mechanisms required by
the various system components.
MCH Power Sequencing
General power sequencing requirements for the Intel 5000P Chipset MCH are simple. In
general higher voltages must come up before lower voltages.
sequencing of the three main voltages powering the Intel 5000P Chipset MCH.
Note:
— G2/S5: Soft off. Requires total system reboot.
— G3: Mechanical Off. All power lost (except real time clock).
Power-up -> 3.3V must ramp ahead and stay above 1.5V, which must ramp ahead and stay above 1.2V.
Figure 5-25
depicts the
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