NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 357

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.14.2.2
5.14.2.3
5.14.3
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
The only system information that will “survive” a PwrGd reset is either contained in
battery-backed or non-volatile storage.
Hard Reset Mechanism
Once the Intel 5000P Chipset MCH platform has been booted and configured, a full
system reset may still be required to recover from system error conditions related to
various device or subsystem failures. The “hard” reset mechanism is provided to
accomplish this recovery without clearing the “sticky” error status bits useful to track
down the cause of system reboot.
A hard reset is typically initiated by the Intel 631xESB/632xESB I/O Controller Hub
component via the PCIRST# output pin, which is commonly connected directly to the
Intel 5000P Chipset MCH RSTIN# input pin. The Intel 631xESB/632xESB I/O Controller
Hub may be caused to assert PCIRST# via both software and hardware mechanisms.
The Intel 5000P Chipset MCH will recognize a hard reset any time RSTIN# is asserted
while PwrGd remains asserted.
The Intel 5000P Chipset MCH will propagate a hard reset to the FSB and to all
subordinate PCI Express subsystems. The FSB components are reset via the
FSBxRESET# signals, while the PCI Express subsystems are reset implicitly when the
root port links are taken down.
A hard reset will clear all internal state machines and logic, and initialize all “non-
sticky” registers to their default states. Note that although the error registers will
remain intact to facilitate root-cause of the hard reset, the Intel 5000P Chipset MCH
platform in general will require a full configuration and initialization sequence to be
brought back on-line.
Processor-Only Reset Mechanism
For power management and other reasons, the Intel 5000P Chipset MCH supports a
targeted processor only reset semantic. This mechanism was added to the platform
architecture to eliminate double-reset to the system when reset-signaled processor
information (such as clock gearing selection) must be updated during initialization
bringing the system back to the S0 state after power had been removed from the
processor complex.
Targeted Reset Mechanism
The targeted reset is provided for Hot-Plug events, as well as for port-specific error
handling under Machine Check Architecture (MCA) or SMI software control. The former
usage model is new with PCI Express technology, and the reader is referred to the PCI
Express Interface Specification, Rev 1.0a for a description of the Hot-Plug mechanism.
A targeted reset may be requested by setting bit 6 (Secondary Bus Reset) of the Bridge
Control Register (offset 3Eh) in the target root port device. This reset will be identical
to a general hard reset from the perspective of the destination PCI Express device; it
will not be differentiated at the next level down the hierarchy. Sticky error status will
survive in the destination device, but software will be required to fully configure the
port and all attached devices once reset and error interrogation have completed. After
clearing bit 6, software may determine when the downstream targeted reset has
effectively completed by monitoring the state of bit 1 (Link Active) of the VS_STS1
register (offset 47h) in the target root port device. This bit will remain deasserted until
the link has regained “link up” status, which implies that the downstream device has
completed any internal and downstream resets, and successfully completed a full
training sequence.
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