NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 359

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
Figure 5-26. Power-On Reset Sequence
Table 5-19. Reset Sequences and Durations
5.15
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
SMBus Interfaces Description
The Intel 5000P Chipset MCH provides six fully functional System Management Bus
(SMBus) Revision 2.0 compliant target interfaces. These interfaces are used to support
platform level operations such as FB-DIMM memory Serial Presence Detect, PCI Hot-
Plug, and configuration of platform devices. Each of these interfaces have dedicated
uses as shown in
Power on
PwrGd
RSTIN#
deassertion
RSTIN#
deassertion
HLA_rstdonecomp
From
HLA_cpurstdone
Hard_Reset
Core_Reset
Cold_Reset
CPURST#
RSTIN#
PwrGd
RSTIN#
deassertion
Hard/Core
deassertion
FSBxRESET#
deassertion
PwrGd
HCLK
To
Figure
5-27.
>2 mS
1 mS
4-6 HCLK
1 mS
Duration
1 mS
Platform
Intel
631xESB/
632xESB
I/O
Controller
Hub
MCH
MCH
Source
4-6 HCLK
Control logic on the platform must ensure that there
are at least 2 mS of stable power before PwrGd is
asserted.
Intel 631xESB/632xESB I/O Controller Hub enforces
delay between detecting PwrGd asserted and
releasing PCIRST# (note that Intel 631xESB/
632xESB I/O Controller Hub PCIRST# is directly
connected to MCH RSTIN#).
MCH waits for a common rising edge on all internal
clocks, then releases core reset(s).
MCH enforces delay between RSTIN# and
FSBxRESET# deassertion. ESI handshake is
incremental to the timer.
1 mS
Comment
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