NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 360

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Figure 5-27. MCH SM Bus Interfaces
5.15.1
360
SM Buses 1, 2, 3 and 4 are dedicated to memory serial presence detect and FB-DIMM
configuration. Each bus is dedicated to a single FB-DIMM channel. SM Bus 1 is assigned
to FB-DIMM channel 0, SM Bus 2 is assigned to FB-DIMM channel 1, SM Bus 3 is
assigned to FB-DIMM channel 2, and SM Bus 4 is assigned to FB-DIMM channel 3. SM
Bus 6 is used to support PCI Express Hot-Plug.
The each SMBus interface consists of two interface pins; one a clock, and the other
serial data. Multiple initiator and target devices may be electrically present on the same
pair of signals. Each target recognizes a start signaling semantic, and recognizes its
own 7-bit address to identify pertinent bus traffic. The MCH address is hard-coded to
01100000b (60h).
The SMBus protocol allows for traffic to stop in “mid sentence,” requiring all targets to
tolerate and properly “clean up” in the event of an access sequence that is abandoned
by the initiator prior to normal completion. The MCH is compliant with this requirement.
The protocol comprehends “wait states” on read and write operations, which the MCH
takes advantage of to keep the bus busy during internal configuration space accesses.
Internal Access Mechanism
All SMBus accesses to internal register space are initiated via a write to the CMD byte.
Any register writes received by the MCH while a command is already in progress will
receive a NAK to prevent spurious operation. The master is no longer expected to poll
the CMD byte to prevent the obliteration a command in progress prior to issuing further
writes. The SMBus access will be delayed by stretching the clock until such time that
the data is delivered. Note that per the System Management Bus (SMBus)
Specification, Rev 2.0, this can not be longer than 25 ms. To set up an internal access,
the four ADDR bytes are programmed followed by a command indicator to execute a
read or write. Depending on the type of access, these four bytes indicate either the Bus
number, Device, Function, Extended Register Offset, and Register Offset, or the
memory-mapped region selected and the address within the region. The configuration
type access utilizes the traditional bus number, device, function, and register offset;
but in addition, also uses an extended register offset which expands the addressable
register space from 256 bytes to 4 Kilobytes. The memory-mapped type access
redefines these bytes to be a memory-mapped region selection byte, a filler byte which
is all zeroes, and then the memory address within the region. Refer to the earlier
ot-plug VPI
aster: PCI-E
aster: SPD
ave: SM Bus
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
SM Bus 6
SM Bus 4
SM Bus 3
SM Bus 2
SM Bus 1
SM Bus 0
JTAG
Intel® 5000P
Chipset
(MCH)
Functional Description