NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 372

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

5.15.5.3
Figure 5-43. Byte Write Register Timing
5.15.5.4
Table 5-24. MCH Supported SPD Protocols
5.15.5.5
5.15.6
372
Request Packet for SPD Byte Write
Upon receiving the SPDW command, the MCH generates the Byte Write Register
command sequence as shown in
has completed by setting the WOD bit of the SPD configuration register to 1.
SPD Protocols
The MCH supports the SPD protocols shown in
SPD Bus Time-out
If there is an error in the transaction, such that the SPD EEPROM does not signal an
acknowledge, the transaction will time out. The MCH will discard the cycle and set the
SBE bit of the SPD configuration register to 1 to indicate this error. The time-out
counter within the MCH begins counting after the last bit of data is transferred to the
DIMM, while the MCH waits for a response.
PCI Express Hot-Plug Support, SM Bus 6
SM Bus 6 is the PCI Express Hot-Plug port. SM Bus 6 is a Hot-Plug Virtual Pin Port (VPP)
that operates using the SM Bus Masters protocol as defined in System Management Bus
Specification 2.0.
SM Bus 6 is dedicated to support PCI Express Hot-Plug devices. Support for PCI
Express is an option described in PCI Express Base Specification, Revision 1.0a. The
PCI Express Hot-Plug model implies a hot-plug controller per port which is identified to
software as a capability of the P2P Bridge configuration space.
PCI Express hot-plug support requires that the Intel 5000P Chipset MCH supports a set
of hot-plug messages (listed in
between the hot-plug controller and the device.
The PCI Express form factor has an impact to the level of support required of the MCH.
For example, some of the hot-plug messages are required only if the LED indicators
reside on the actual card and are accessed through the endpoint device. The Intel
5000P Chipset MCH supports all of the hot-plug messages so that the platform is not
constrained to any particular form factor.
MCH Supported SPD
Random Byte Read
Protocols
Byte Write
A
R
S
T
T
D
T
3
I
Slave Address
D
T
2
I
D
T
1
I
D
T
0
I
S
A
2
S
A
1
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
S
A
0
W
R
/
Figure 5-14
Figure
A
C
K
0
B
A
7
B
A
6
Byte Address
B
A
5
5-43. The MCH indicates that the SIO command
B
A
4
B
A
3
and
B
A
2
Table
B
A
1
Figure
B
A
0
A
C
K
5-24.
5-20) to manage the states
DATA
Functional Description
A
C
K
O
S
T
P