NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 38
NQ5000P S L9TN
Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet
1.NQ5000P_S_L9TN.pdf
(530 pages)
Specifications of NQ5000P S L9TN
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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2.10
2.10.1
2.10.1.1
Figure 2-2.
2.10.1.2
Figure 2-3.
2.10.1.3
38
PCI-Express Compatibility
PCI-Express Compatibility
Synchronized RESETI#
Synchronized RESETI#
processor RESET#
processor RESET#
PCI-Express
Power Rails
PWRGOOD
PWRGOOD
Reset Requirements
Timing Diagrams
Power-Up
The power-up sequence is illustrated in
Power-Up
Power Good
The PWRGOOD reset sequence is illustrated in
PWRGOOD
Hard Reset
The Hard Reset sequence is illustrated in
Sticky Bits
Express
RESETI#
BUSCLK
RESETI#
BUSCLK
PCI-
Events
Events
PLL's
PLL's
POC
POC
FBD
FBD
Internal power detect
T2
Straps
active
T1
Non-FBD Analog
compensation
completed
T3
sampled
Straps
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
sampled
Straps
T7
T7
T8
T8
T10
T10
T9
T9
inactive
inactive
Straps
Straps
Figure
downloaded
downloaded
Reset
Reset
Figure
Fuses
Fuses
2-2.
Figure
T11
T11
2-4.
T17
initialization
T17
initialization
T12
T12
2-3.
Array Init
Array Init
T13
T13
Done
Init
Done
Init
full operation
full operation
T14
T15
T14
T15
Level
Level
Signal Description
DMI handshake done
DMI handshake done
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