NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 381

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.16.6.6
5.16.6.7
5.16.6.8
5.17
Table 5-31. Intel 5000P Chipset Error List (Sheet 1 of 7)
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
F1
F2
F5
in MCH
ERR #
Request/
Address Parity
Error
Unsupported
Request or
data size on
FSB.
Outstanding
Deferred FSB
transaction
has timed out
Error Name
Other PLL Characteristics
The PLL VCOs oscillate continually from power-up. The PLL output dividers consistently
track the VCO, providing pulses to the clock trees. Logic that does not receive an
asynchronous reset can thus be reset “synchronously”.
A “locked” PLL will only serve to prove that the feedback loop is continuous. It will not
prove that the entire clock tree is continuous.
Analog Power Supply Pins
The Intel 5000P Chipset MCH incorporates seven PLLs. Each PLL requires an Analog Vcc
and Analog Vss pad and external LC filter. Therefore, there will be external LC filters for
the Intel 5000P Chipset MCH. IMPORTANT: The filter is NOT to be connected to board
Vss. The ground connection of the filter will be routed through the package and
grounded to on-die Vss.
I/O Interface Metastability
PCI Express can be operated frequency-locked to the core. Flits are fifteen-sixteenths
of the core frequency in 266 MHz mode, three-quarters of the core frequency in
333 MHz mode.
However, the phase between the frequency-locked domains is not controlled. This
scheme results in the possibility of a metastability resonance where, for example, the
commands generated by the core miss setup and hold to I/O every time. This condition
can be tolerated by carefully hardened metastability design.
Error List
This section provides a summary of errors detected by the Intel 5000P Chipset. In the
following table, errors are listed by the unit / interfaces. Some units / interfaces may
provide additional error logging registers.
The following table provides the list of detected errors of a the MCH.
MCH monitors the address
and request parity signals
on the FSB. A parity
discrepancy over these
fields during a valid
request. MCH only detects
this error caused by CPUs.
MCH detected an FSB
Unsupported transaction.
MCH only detects this error
caused by CPUs.
MCH detected that a
previously deferred FSB txn
has not completed with
Defer Reply within a
specified time frame.
Definition
Fatal
Fatal
Fatal
Error
Type
FERR_FAT_FSB/
NERR_FAT_FSB. NRECFSB,
NRECFSB_ADDRH,
NRECFSB_ADDRL for FERR
only.
FERR_FAT_FSB/
NERR_FAT_FSB. NRECFSB
for FERR only.
FERR_FAT_FSB/
NERR_FAT_FSB. NRECFSB
for FERR only
Log Register
Complete transaction on FSB
with response (non-hard fail
response)
Treat as NOP. No Data
Response or Retry by MCH
An access issued on the FSB
has timed out.
Cause / Actions
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