NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 397

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Intel® 5000V Chipset Differences
7
7.1
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Intel
Differences
The Intel
at value segment servers. It features an interface set that is optimized for high volume
low cost server implementations.Intel 5000V Chipset supports a common programming
model with other members of the Intel 5000P Chipset family.
Intel 5000V Chipset Overview
Figure 7-1
The Intel 5000V Chipset is designed for use in server systems based on the processor
Dual-Core Intel Xeon 5000 Sequence processor. The Intel 5000V Chipset supports two
processors on dual independent point to point system buses operating at 266 MHz
(1066 MTS) or two processors on dual independent point to point system buses
operating at 333 MHz (1333 MTS). The theoretical bandwidth of the two processor
busses is 17 GB/s for Dual-Core Intel Xeon 5000 series and 21GB/s for Dual-Core Intel
Xeon 5100 series.
In an Intel 5000V Chipset-based platform, the MCH provides the processor interface,
fully buffered DIMM memory interfaces, PCI Express bus interfaces, ESI interface, and
SM Bus interfaces.
The MCH provides two channels of fully buffered DIMM (FB-DIMM) memory. Each
channel can support up to 4 DIMMs. FB-DIMM memory channels are organized in to a
single branch. The MCH can support up to 8 DIMM or a maximum memory size of
16 GB. The read bandwidth for each FB-DIMM channel is 4.25 GB/s for DDR2 533
FB-DIMM memory which gives a total read bandwidth of 8.5 GB/s for two FB-DIMM
channels. Thus, this provides 2.125 GB/s of write memory bandwidth for two FB-DIMM
channels. The read bandwidth for each FB-DIMM channel is 5.35 GB/s for DDR2
667 FB-DIMM memory which gives a total read bandwidth of 10.7 GB/s for two
FB-DIMM channels. Thus, this provides 2.65 GB/s of write memory bandwidth for two
FB-DIMM channels. The total bandwidth is based on read bandwidth thus the total
bandwidth is 8.5 GB/s for 533 and 10.7 GB/s for 667.
The Intel 631xESB/632xESB I/O Controller Hub integrates an Ultra ATA 100 controller,
six Serial ATA host controller ports, one EHCI host controller, and four UHCI host
controllers supporting eight external USB 2.0 ports, LPC interface controller, and a flash
BIOS interface controller. Additionally the Intel 631xESB/632xESB I/O Controller Hub
contains a PCI interface controller, Azalia / AC’97 digital controller, integrated LAN
controller, an ASF controller and a ESI for communication with the MCH. The Intel
631xESB/632xESB I/O Controller Hub component provides the data buffering and
interface arbitration required to ensure that system interfaces operate efficiently and
provide the bandwidth necessary to enable the system to obtain peak performance.
The Intel 631xESB/632xESB I/O Controller Hub elevates Serial ATA storage
performance to the next level with Intel® RAID.
The ACPI compliant Intel 631xESB/632xESB I/O Controller Hub platform can support
the Full-on, Stop Grant, Suspend to RAM, Suspend to Disk, and Soft-Off power
management states. Through the use of the integrated LAN functions, the Intel
631xESB/632xESB I/O Controller Hub also supports Alert Standard Format for remote
management.
®
shows an example block diagram of a Intel 5000P Chipset-based platform.
5000V chipset MCH is a member of the Intel 5000P Chipset family targeted
®
5000V Chipset
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