NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 4

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

4
3.8
3.9
3.10
Register Definitions ............................................................................................74
3.8.1
3.8.2
3.8.3
3.8.4
3.8.5
3.8.6
3.8.7
3.8.8
3.8.9
3.8.10 PCI Express Message Signaled Interrupts (MSI) Capability Structure............ 133
3.8.11 PCI Express Capability Structure ............................................................. 138
3.8.12 PCI Express Advanced Error Reporting Capability ...................................... 159
3.8.13 Error Registers ..................................................................................... 181
Memory Control Registers ................................................................................. 192
3.9.1
3.9.2
3.9.3
3.9.4
3.9.5
3.9.6
3.9.7
3.9.8
3.9.9
3.9.10 FBDTOHOSTGRCFG0: FB-DIMM to Host Gear Ratio Configuration 0.............. 198
3.9.11 FBDTOHOSTGRCFG1: FB-DIMM to Host Gear Ratio Configuration 1.............. 199
3.9.12 HOSTTOFBDGRCFG: Host to FB-DIMM Gear Ratio Configuration .................. 200
3.9.13 GRFBDVLDCFG: FB-DIMM Valid Configuration ........................................... 200
3.9.14 GRHOSTFULLCFG: Host Full Flow Control Configuration.............................. 202
3.9.15 GRBUBBLECFG: FB-DIMM Host Bubble Configuration ................................. 202
3.9.16 GRFBDTOHOSTDBLCFG: FB-DIMM To Host Double Configuration ................. 203
3.9.17 Summary of Memory Gearing Register operating modes ............................ 203
3.9.18 DRTA - DRAM Timing Register A ............................................................. 203
3.9.19 DRTB - DDR Timing Register B ............................................................... 205
3.9.20 ERRPER - Error Period ........................................................................... 206
3.9.21 Memory Map Registers .......................................................................... 206
3.9.22 FB-DIMM Error Registers........................................................................ 208
3.9.23 FB-DIMM Branch Registers ..................................................................... 223
3.9.24 FB-DIMM RAS Registers......................................................................... 232
3.9.25 FB-DIMM IBIST Registers....................................................................... 235
3.9.26 Serial Presence Detect Registers ............................................................. 251
DMA Engine Configuration Registers ................................................................... 252
3.10.1 PCICMD: PCI Command Register ............................................................ 252
3.10.2 PCISTS: PCI Status Register .................................................................. 254
3.10.3 CCR: Class Code Register ...................................................................... 255
3.10.4 CB_BAR: DMA Engine Base Address Register ............................................ 255
3.10.5 CAPPTR: Capability Pointer Register ........................................................ 256
3.10.6 INTL: Interrupt Line Register.................................................................. 256
3.10.7 INTP: Interrupt Pin Register ................................................................... 256
3.10.8 Power Management Capability Structure .................................................. 256
3.10.9 MSICAPID - Message Signalled Interrupt Capability ID Register................... 259
3.10.10MSINXPTR - Message Signalled Interrupt Next Pointer Register ................... 259
3.10.11MSICTRL - Message Signalled Interrupt Control Register ............................ 259
3.10.12MSIAR: Message Signalled Interrupt Address Register ............................... 261
3.10.13MSIDR: Message Signalled Interrupt Data Register.................................... 261
3.10.14PEXCAPID: PCI Express Capability ID Register .......................................... 262
PCI Standard Registers............................................................................74
Address Mapping Registers ......................................................................83
AMB Memory Mapped Registers ................................................................92
Interrupt Redirection Registers .................................................................95
Boot and Reset Registers .........................................................................97
Control and Interrupt Registers .............................................................. 100
PCI Express Device Configuration Registers .............................................. 102
PCI Express Header .............................................................................. 104
PCI Express Power Management Capability Structure................................. 131
MC - Memory Control Settings ................................................................ 192
GBLACT - Global Activation Throttle Register ............................................ 194
THRTSTS[1:0] - Thermal Throttling Status Register................................... 195
THRTLOW - Thermal Throttling Low Register ............................................ 196
THRTMID - Thermal Throttle Mid Register ................................................ 196
THRTHI - Thermal Throttle High Register ................................................. 197
THRTCTRL - Thermal Throttling Control Register ....................................... 197
MCA - Memory Control Settings A ........................................................... 197
DDRFRQ - DDR Frequency Ratio ............................................................. 198
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet