NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 40

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

2.10.2
Table 2-3.
a. In the Intel 5000P chipset B0 RTL, the T11 duration is implemented through a counter with max value of 162,000 core clocks.
40
Notes:
Timing
T10
T11
T12
T13
T14
T15
T16
T17
For 333 Mhz, this gives a period of 486 us for the POC setup time while @266 Mhz, the period is 607.5 us.
T1
T2
T3
T4
T5
T7
T8
T9
Power and master clocks stable to
PWRGOOD signal assertion
PWRGOOD de-assertion to straps active
PWRGOOD de-assertion
POC after RESET# assertion delay
Platform reset de-assertion to platform
reset assertion
PWRGOOD assertion to POC active
PWRGOOD assertion to straps inactive
RESETI# signal assertion during PWRGOOD
/ PWROK signal assertion
RESET# assertion during processor
PWRGOOD assertion
RESETI# signal de-assertion to processor
RESET# signal de-assertion
RESETI# signal de-assertion to completion
of PCI-Express initialization sequence
Array Initialization duration
POC hold time after RESET# de-assertion
Initiation of DMI reset sequence to
processor RESET# signal de-assertion
RESETI# re-trigger delay
CPU_RESET_DONE capture timer
Reset Timing Requirements
Table 2-3
Figure
clock frequencies.
Power Up and Hard Reset Timings
Description
2-5. Nominal clock frequencies are described. Specifications still hold for derated
specifies the timings drawn in
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
2ms
80ns
1 BUSCLK
50 BUSCLK’s
2 BUSCLK’s
12ns
1ms
1ms
480us
2 BUSCLK’s
T5 + T9
2,000 BUSCLK’s
a
Min
Figure
40ns
18ns
10ms
1,250,000
PECLK’s
200 cycles
19 BUSCLK’s
10,000 PECLK’s
+ T17
2-2,
Max
Figure
3GIO PLL specification
Minimum PWRGOOD de-assertion
time while power and platform
clocks are stable.
Minimum re-trigger time on
RESETI# de-assertion.
POC turn-on delay after strap
disable
Strap Hold Time
This delay can be provided by the
ICH6 or by system logic
Processor EMTS specification.
Note: This is a special Dual-Core
Intel Xeon 5100 series requirement
to have a longer POC assertion
setup time on the FSB and the
Intel® 5000P chipset has added a
fix in B0 RTL to increase this time
period from 160us to 480us.
PCI-Express clock is 100MHz
Processor EMTS specification
ICH6 specification
2-3,
Figure
Comments
2-4, and
Signal Description