NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 400

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Intel® 5000V Chipset Differences
SM Buses 1 and 2 are dedicated to memory serial presence detect and FB-DIMM
configuration. SM Bus 6 is used to support PCI Express Hot-Plug.
The each SMBus interface consists of two interface pins; one a clock, and the other
serial data. Multiple initiator and target devices may be electrically present on the same
pair of signals. Each target recognizes a start signaling semantic, and recognizes its
own 7-bit address to identify pertinent bus traffic. The MCH address is hard-coded to
01100000b (60h).
The SMBus protocol allows for traffic to stop in “mid sentence,” requiring all targets to
tolerate and properly “clean up” in the event of an access sequence that is abandoned
by the initiator prior to normal completion. The MCH is compliant with this requirement.
The protocol comprehends “wait states” on read and write operations, which the MCH
takes advantage of to keep the bus busy during internal configuration space accesses.
The SM Bus register model for the Intel 5000V Chipset is the same as that for Intel
5000P Chipset with the exception that SM Buses 3, and 4 do not exist.
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Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet