NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 401

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Testability
8
8.1
8.1.1
8.1.2
Table 8-1.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Testability
JTAG Port
Each component in the Intel 5000P Chipset includes a Test Access Port (TAP) slave
which complies with the IEEE 1149.1 (JTAG) test architecture standard. Basic
functionality of the 1149.1- compatible test logic is described here, but this document
does not describe the IEEE 1149.1 standard in detail. For this, the reader is referred to
the published standard
JTAG Access to Configuration Space
JTAG has become a name that is synonymous with the IEEE 1149.1 test access port
(TAP). Besides the boundary scan capabilities for low speed buses and pins, it provides
an inexpensive serial interface port to up/download data to and from the chip.
Throughout this document any reference to JTAG will imply the test access port (TAP)
and the private chains that it is connected too, unless specifically mentioning the
boundary scan attributes.
The feature described here is a JTAG private data chain that initiate a configuration
request to the components configuration arbitration logic. During platform debug it is
helpful to have a back door access to register space to determine correct configuration
states. The In-Target Probe (ITP) provides an effective observation capability that links
the hardware and the user together to examine and control a number of DFT and
debug features.
Access to a component’s configuration space must be non-blocking to a JTAG initiated
configuration request to the Intel 5000P Chipset MCH’s register space. Since the Intel
5000P Chipset MCH can source configuration transactions to other components and an
errant configuration transaction that could potentially hang the system and prevent a
JTAG access to the Intel 5000P Chipset MCH’s configuration space. An additional chain
is provided to ensure the ITP tool has unconditional access privilege to the Intel 5000P
Chipset MCH in case there are configuration transaction hangs from another source.
TAP Signals
The TAP logic is accessed serially through 5 dedicated pins on each component as
shown in
TAP Signal Definitions
TMS, TDI and TDO operate synchronously with TCK (which is independent of all other
clocks). TRST# is an asynchronous reset input signal. This 5-pin interface operates as
defined in the 1149.1 specification. A simplified block diagram of the TAP used in the
Intel 5000P Chipset components is shown in
TCK
TMS
TDI
TDO
TRST#
Table
8-1.
TAP Clock input
Test Mode Select. Controls the TAP finite state machine.
Test Data Input. The serial input for test instructions and data.
Test Data Output. The serial output for the test data.
Test Reset input.
1
, and to the many books currently available on the subject.
Figure
8-1.
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