NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 408

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

8.1.10
Table 8-4.
8.1.11
8.1.11.1
Figure 8-7.
8.1.12
412
Public Data Register Control
Table 8-4
that can alter data register contents. If a TAP state does not affect the selected data
register, then the corresponding table entry will be blank. Not all data registers have a
parallel output latch. All data registers have a parallel input latch. Several table entries
are still under investigation.
Actions of Public TAP Instructions During Various TAP States
Bypass Register
This register provides the minimal length path between TDI and TDO. It is loaded with a
logical 0 during the Capture-DR state. The Bypass Register is a single bit register and is
used to provide a minimum-length serial path through the device. This allows more
rapid movement of test data to and from other components in the system. When in
Bypass Mode, the operation of the test logic shall have no effect on the operation of the
devices normal logic. Refer to
Bypass Register Definition
Bypass Register Implementation
Device ID Register
This register contains the device identification code in the format shown in
Three fields are predefined as the version number (stepping number), the
manufacturer’s identification code, and a logical 1 field. The component identification
field is sub-divided into 3 fields. The Product Segment field identifies if the component
is intended for CPU, laptop, desktop, server, etc. Product Type further defines the
Bypass
HighZ
IDcode
Extest
Sample/Preload
Instruction
define the actions that occur in the selected data register in controller states
Reset Bypass Register
Reset Bypass Register
Load device ID into
register
Load input pin values into
Boundary Scan shift
register
Load pin values into
Boundary Scan shift
register
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Capture-DR
Figure 8-7
for an implementation example.
Shift Bypass register
Shift Bypass register
Shift ID register
Shift Boundary Scan shift
register
Shift Boundary Scan shift
register
Shift-DR
Load Boundary Scan shift
register into Boundary
Scan register; drive pins
accordingly
Load Boundary Scan shift
register into Boundary
Scan register
Update-DR
Table 8-5
Testability