NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 41

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NQ5000P S L9TN

Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet

Specifications of NQ5000P S L9TN

Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Signal Description
Table 2-4.
2.10.3
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Table 2-4
Critical Intel® 5000P Initialization Timings
Miscellaneous Requirements and Limitations
Intel® 5000P chipset Core,
FSB, FB-DIMM PLL lock
Intel® 5000P MCH PCI Express
PLL lock
Array initialization
Fuse download
• Power rails and stable BUSCLK, FBD{0/1}CLK, and PECLK master clocks remain
• Frequencies (for example, 266 MHz) described in this chapter are nominal. The
• Hard Reset can be initiated by code running on a processor, JTAG, SMBus, or PCI
• Hard Reset is not guaranteed to correct all illegal configurations or malfunctions.
• System activity is initiated by a request from a processor bus. No I/O devices will
• The FB-DIMM channels will be enabled for packet levelization (Intel 5000P
• The default values of the POC configuration register bits do not require any
• Cleanly aborting an in-progress SPD command during a PWRGOOD deassertion is
within specifications through all but power-up reset.
Intel 5000P chipset MCH reset sequences must work for the frequency of operation
range specified in the Clocking chapter.
agents.
Software can configure sticky bits in the Intel 5000P chipset MCH to disable
interfaces that will not be accessible after Hard Reset. Signaling errors or protocol
violations prior to reset (from processor bus, FB-DIMM, or PCI Express) may hang
interfaces that are not cleared by Hard Reset.
initiate requests until configured by a processor to do so.
MCH.FBDST.STATE=“Ready” or “RecoveryReady” state) upon completion of a hard
reset. Software should inspect the Intel 5000P chipset MCH.FBDST.STATE
configuration bits to determine which FB-DIMM channels are available.
processor request signals to be asserted when PWRGOOD is first asserted.
Software sets these configuration registers to define these values, then initiates a
hard reset that causes them to be driven during processor RESET# signal
assertion.
problematic. No guarantee can be issued as to the final state of the EEPROM in this
situation. The Intel® 5000P MCH cannot meet the SPD data t
specification. Since the Intel® 5000P MCH floats the data output into a pull-up on
the platform, a read will not degrade to a write. However, if the PWRGOOD
deassertion occurs after the EEPROM has received the write bit, the data will be
corrupted. The platform pull-up must be strong enough to complete a low-to-high
transition on the clock signal within t
specification) after deassertion of PWRGOOD to prevent clock glitches. Within these
constraints, an in-progress write address will not be corrupted.
Sequence
summarizes the Product Name Initialization timings.
Stable power and master clock
Stable power and master clock
Synchronized RESETI#
Deassertion
PWRGOOD Assertion
Started by
R
= 1 microsecond (ATMEL AT24C01 timing
666,667 333 MHz cycles
200,000 100 MHz cycles
200 cycles
333,333 333 MHz cycles
Maximum Length
SU,STO
timing
T
T
T
Covered by
parameter
1
17
9
Timing
41

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