NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 414

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

9.2
9.3
9.4
9.5
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Fully Buffered DIMM (FB-DIMM) Memory
Intel 5000Z Chipset supports two channels of FB-DIMM DDR2 memory organized in one
branch. Each channel supports 4 DIMMs for a total of 8 DIMMs. The 8 DIMMs will
support a maximum of 16 GB physical memory when using DIMMs fabricated with
2 Gbit DDR2 components.
Since only one branch exists on the Intel 5000Z Chipset MCH, RAID 1 mirroring is not
possible.
The Intel 5000Z Chipset uses the same register programming model as the Intel 5000P
Chipset MCH with the exception that the FBD branch1 registers do not exist.
ESI Port
The Intel 5000Z Chipset ESI port supports the same functionality as the Intel 5000P
Chipset ESI port. The resister models are the same.
PCI Express Ports
Intel 5000Z Chipset supports four x4 ports of PCI Express. These four ports are
designated ports 2, 3, 4, and 5. These four x4 ports may be combined to form two
single x8 PIC Express port (Port 2,3 and port 4,5).
Ports 2 and 3 are normally used to supplement the bandwidth of the ESI port to the
Intel 631xESB/632xESB I/O Controller Hub South bridge. Ports 2, 3, 4, and 5 may be
used to interface PCI Express connectors or down devices.
The register model for Intel 5000Z Chipset ports 2, 3, 4, and 5 is the same as Intel
5000P Chipset with DMA engine supported. Unlike the Intel 5000P Chipset MCH, the
Intel 5000Z Chipset does not have PCI Express ports 6, and 7.
Register Definitions
Intel 5000Z Chipset Register Definitions are the same as the Intel 5000V Chipset with
the exception that the following Register Definitions should be added.
PCI Standard Registers
VID - Vendor Identification Register
DID - Device Identification Register
RID - Revision Identification Register
CCR - Class Code Register
HDR - Header Type Register
PCI Express Header
PCICMD[7:2, 0]- Command Register
PCISTS[7:2, 0] - Status Register
CLS[7:2, 0] - Cache Line Size
PRI_LT[7:2, 0] - Primary Latency Timer
BIST[7:2,0] - Built-In Self Test
Register Name
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
Device
Intel® 5000Z Chipset Differences
0
0
0
0
0
0
0
0
0
0
Function
00h
02h
08h
09h
0Eh
04h
06h
0Ch
0Dh
0Fh
Offset