NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 48

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Figure 3-1.
3.3
48
Conceptual Intel 5000P Chipset MCH PCI Configuration Diagram
Routing Configuration Accesses
The Intel 5000P Chipset MCH supports both PCI Type 0 and Type 1 configuration access
mechanisms as defined in the PCI Local Bus Specification, Revision 2.3. PCI Revision
2.3 defines hierarchical PCI busses. Type 0 configuration access are used for registers
located within a PCI device that resides on the local PCI bus. That is, the PCI bus the
• Device 22: Device 22, Function 0, FBD Branch 1 Memory Map, Error Flag/Mask,
and Channel Control registers. These devices reside at DID 25F6h.
PCI Express
PCI Express
PCI Express
PCI Express
Port 4
Port 5
Port 6
Port 7
4 bit
4 bit
4 bit
4 bit
Intel® 631xESB/632xESB I/O Controller Hub
Intel® 5000X
Chipset
Bus 0, Dev 31, Func 0
Bus 0, Dev 31, Func 1
Bus 0, Dev 31, Func 3
Bus 0, Dev 31, Func 5,6
Bridge Bus 0, Dev 4
Bridge Bus 0, Dev 5
Bridge Bus 0, Dev 6
Bridge Bus 0, Dev 7
PCI Express Port 4
PCI Express Port 5
PCI Express Port 6
PCI Express Port 7
SMBus Controller
AC97 Controller
IDE Controller
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Processor 0
LPC Device
PCI Config Window in I/O Space
(PCI Express Bridge Bus 0,
(PCI Express Bridge Bus 0,
Dev 0)
Dev X)
DMI
DMI
DMI Interface (logical PCI Bus 0)
Bus 0, Dev 30, Func 0
Bus n, Dev 8, Func 0
Bridge Bus 0, Dev Y
Bridge Bus 0, Dev Z
Bridge Bus 0, Dev 2
Bridge Bus 0, Dev 3
PCI Express Port 2
PCI Express Port 3
PCI Express Port 0
PCI Express Port 1
USB Controllers
LAN Controller
Processor 1
HI-PCI Bridge
Bus 0, Dev 29,
Func 0,1,2,7
PCI Express
PCI Express
PCI Express
PCI Express
Programmable
Primary PCI
Port 0
Port 0
Port 2
Port 3
4 bit
4 bit
4 bit
4 bit
Bus #
Register Description