NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 5

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

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Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
3.11
System Address Map................................................................................................. 275
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Functional Description ............................................................................................... 297
5.1
5.2
3.10.15PEXNPTR: PCI Express Next Pointer Register............................................ 262
3.10.16PEXCAPS - PCI Express Capabilities Register ............................................ 263
3.10.17PEXDEVCAP - Device Capabilities Register ............................................... 263
3.10.18PEXDEVCTRL - Device Control Register.................................................... 264
3.10.19 PEXDEVSTS - PCI Express Device Status Register .................................... 265
PCI Express IBIST Registers ............................................................................. 266
3.11.1 DIOIBSTR: PCI Express IBIST Global Start/Status Register ........................ 266
3.11.2 DIO0IBSTAT: PCI Express IBIST Completion Status Register ...................... 267
3.11.3 DIO0IBERR: PCI Express IBIST Error Register .......................................... 267
3.11.4 PEX[7:2,0]IBCTL: PEX IBIST Control Register .......................................... 268
3.11.5 PEX[7:2,0]IBSYMBUF: PEX IBIST Symbol Buffer ....................................... 269
3.11.6 PEX[7:2,0]IBEXTCTL: PEX IBIST Extended Control Register ....................... 270
3.11.7 PEX[7:2,0]IBDLYSYM: PEX IBIST Delay Symbol........................................ 272
3.11.8 PEX[7:2,0]IBLOOPCNT: PEX IBIST Loop Counter ...................................... 272
3.11.9 PEX[7:2,0]IBLNS[3:0]: PEX IBIST Lane Status......................................... 273
3.11.10DIO[1:0]SQUELCH_CNT: PCIe Cluster Squelch Count................................ 274
System Memory Address Ranges ....................................................................... 276
4.1.1
Compatibility Area ........................................................................................... 278
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
System Memory Area....................................................................................... 281
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
Memory Address Disposition ............................................................................. 287
4.4.1
4.4.2
4.4.3
I/O Address Map ............................................................................................. 293
4.5.1
4.5.2
Configuration Space ........................................................................................ 295
I/O Address Map ............................................................................................. 295
4.7.1
4.7.2
Configuration Space ........................................................................................ 296
Processor Front Side Buses ............................................................................... 297
5.1.1
5.1.2
5.1.3
System Memory Controller ............................................................................... 298
5.2.1
5.2.2
32/64-bit addressing ............................................................................ 276
MS-DOS Area (0 0000h–9 FFFFh) ........................................................... 278
Legacy VGA Ranges (A 0000h–B FFFFh) .................................................. 279
Expansion Card BIOS Area (C 0000h–D FFFFh)......................................... 280
Lower System BIOS Area (E 0000h–E FFFFh) ........................................... 280
Upper System BIOS Area (F 0000h–F FFFFh) ........................................... 281
System Memory ................................................................................... 281
15 MB - 16 MB Window (ISA Hole).......................................................... 281
Extended SMRAM Space (TSEG) ............................................................. 281
Memory Mapped Configuration (MMCFG) Region ....................................... 282
Low Memory Mapped I/O (MMIO) ........................................................... 283
Chipset Specific Range .......................................................................... 284
Interrupt/SMM Region........................................................................... 284
High Extended Memory ......................................................................... 286
Main Memory Region ............................................................................ 287
Registers Used for Address Routing......................................................... 287
Address Disposition for Processor ........................................................... 288
Inbound Transactions ........................................................................... 291
Special I/O Addresses ........................................................................... 293
Outbound I/O Access ............................................................................ 293
Special I/O Addresses ........................................................................... 295
Outbound I/O Access ............................................................................ 296
FSB Overview ...................................................................................... 297
FSB Dynamic Bus Inversion ................................................................... 297
FSB Interrupt Overview......................................................................... 298
Memory Population Rules ...................................................................... 300
Fully Buffered DIMM Technology and Organization .................................... 303
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