NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 6

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

6
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
5.2.10 FB-DIMM Memory Failure Isolation Mechanisms ........................................ 311
5.2.11 DDR2 Protocol ...................................................................................... 315
5.2.12 Memory Thermal Management................................................................ 315
5.2.13 Electrical Throttling ............................................................................... 326
Intel 5000P Chipset Behavior on Overtemp State in AMB....................................... 326
Interrupts ....................................................................................................... 327
XAPIC Interrupt Message Delivery...................................................................... 327
5.5.1
5.5.2
5.5.3
5.5.4
I/O Interrupts ................................................................................................. 331
5.6.1
5.6.2
5.6.3
5.6.4
Interprocessor Interrupts (IPIs) ......................................................................... 333
Chipset Generated Interrupts ............................................................................ 335
5.8.1
Legacy/8259 Interrupts .................................................................................... 339
Interrupt Error Handling ................................................................................... 339
Enterprise South Bridge Interface (ESI) .............................................................. 340
5.11.1 Power Management Support................................................................... 341
5.11.2 Special Interrupt Support....................................................................... 341
5.11.3 Inbound Interrupts ............................................................................... 341
5.11.4 Legacy Interrupt Messages .................................................................... 342
5.11.5 End-of-Interrupt (EOI) Support .............................................................. 342
5.11.6 Error Handling...................................................................................... 342
PCI Express Ports ............................................................................................ 342
5.12.1 Intel 5000P Chipset MCH PCI Express Port Overview ................................. 343
5.12.2 Enterprise South Bridge Interface (ESI) ................................................... 344
5.12.3 PCI Express Ports 2 and 3 ...................................................................... 344
5.12.4 PCI Express General Purpose Ports.......................................................... 345
5.12.5 Supported Length Width Port Partitioning ................................................. 346
5.12.6 PCI Express Port Support Summary ........................................................ 347
5.12.7 PCI Express Port Physical Layer Characteristics ......................................... 348
5.12.8 Link Layer............................................................................................ 350
5.12.9 Flow Control......................................................................................... 352
5.12.10Transaction Layer ................................................................................. 354
Power Management.......................................................................................... 354
5.13.1 Supported ACPI States .......................................................................... 354
5.13.2 FB-DIMM Thermal Management .............................................................. 355
5.13.3 FB-DIMM Thermal Diode Overview .......................................................... 355
System Reset.................................................................................................. 355
5.14.1 MCH Power Sequencing ......................................................................... 355
5.14.2 MCH Reset Types.................................................................................. 356
5.14.3 Targeted Reset Mechanism .................................................................... 357
5.14.4 BINIT# Mechanism ............................................................................... 358
5.14.5 Reset Sequencing ................................................................................. 358
FB-DIMM Memory Operating Modes......................................................... 305
Data Poisoning in Memory...................................................................... 307
Patrol Scrubbing ................................................................................... 307
Demand Scrubbing ............................................................................... 308
x8 Correction ....................................................................................... 308
Single Device Data Correction (SDDC) Support ......................................... 309
FB-DIMM Memory Configuration Mechanism ............................................. 309
XAPIC Interrupt Message Format ............................................................ 327
XAPIC Destination Modes ....................................................................... 328
Interrupt Redirection ............................................................................. 329
EOI..................................................................................................... 331
Ordering.............................................................................................. 331
Hardware IRQ IOxAPIC Interrupts ........................................................... 332
Message Signalled Interrupts ................................................................. 332
Non-MSI Interrupts - “Fake MSI” ............................................................ 332
Intel 5000P Chipset Generation of MSIs ................................................... 337
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet