NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 7

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

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Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
5.15
5.16
5.17
Electrical Characteristics............................................................................................ 393
6.1
6.2
Intel® 5000V Chipset Differences ............................................................................... 401
7.1
7.2
7.3
7.4
7.5
Testability ............................................................................................................... 405
8.1
8.2
Intel® 5000Z Chipset Differences ............................................................................... 415
9.1
9.2
9.3
SMBus Interfaces Description............................................................................ 359
5.15.1 Internal Access Mechanism .................................................................... 360
5.15.2 SMBus Transaction Field Definitions ........................................................ 361
5.15.3 SMB Transaction Pictographs ................................................................. 364
5.15.4 Slave SM Bus, SM Bus 0........................................................................ 366
5.15.5 FB-DIMM SPD Interface, SM Buses 1, 2, 3 and 4 ...................................... 371
5.15.6 PCI Express Hot-Plug Support, SM Bus 6 ................................................. 372
5.15.7 Hot-Plug Controller ............................................................................... 373
5.15.8 PCI Express Hot-Plug Usage Model.......................................................... 373
5.15.9 Virtual Pin Ports ................................................................................... 374
Clocking......................................................................................................... 377
5.16.1 Reference Clocks.................................................................................. 377
5.16.2 JTAG .................................................................................................. 379
5.16.3 SMBus Clock........................................................................................ 379
5.16.4 GPIO Serial Bus Clock ........................................................................... 379
5.16.5 Clock Pins ........................................................................................... 379
5.16.6 High Frequency Clocking Support ........................................................... 380
Error List........................................................................................................ 381
Absolute Maximum Ratings............................................................................... 393
6.1.1
6.1.2
DC Characteristics ........................................................................................... 394
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
Intel 5000V Chipset Overview ........................................................................... 401
Fully Buffered DIMM (FB-DIMM) Memory ............................................................ 403
ESI Port ......................................................................................................... 403
PCI Express Ports ............................................................................................ 403
System Management Bus Interfaces .................................................................. 403
JTAG Port ....................................................................................................... 405
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.1.8
8.1.9
8.1.10 Public Data Register Control................................................................... 412
8.1.11 Bypass Register ................................................................................... 412
8.1.12 Device ID Register................................................................................ 412
8.1.13 Boundary Scan Register ........................................................................ 413
Extended Debug Port (XDP) .............................................................................. 414
Intel 5000Z Chipset Overview ........................................................................... 415
Fully Buffered DIMM (FB-DIMM) Memory ............................................................ 418
ESI Port ......................................................................................................... 418
Thermal Characteristics......................................................................... 393
Power Characteristics............................................................................ 393
Clock DC Characteristics........................................................................ 395
FSB Interface DC Characteristics ............................................................ 396
FB-DIMM DC Characteristics .................................................................. 397
PCI Express/ ESI Interface DC Characteristics .......................................... 398
Miscellaneous DC Characteristics ............................................................ 399
JTAG Access to Configuration Space........................................................ 405
TAP Signals ......................................................................................... 405
Accessing the TAP Logic ........................................................................ 406
Reset Behavior of the TAP ..................................................................... 408
Clocking the TAP .................................................................................. 408
Accessing the Instruction Register .......................................................... 408
Accessing the Data Registers ................................................................. 410
Public TAP Instructions.......................................................................... 410
Public Data Instructions ........................................................................ 411
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