NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 79

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
Figure 3-3.
3.8.1.4
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
The CRID is not a directly addressable PCI register. The CRID value is reflected through
the RID register when appropriately addressed.The 4 bits of the CRID are reflected as
the two least significant bits of the major and minor revision field respectively. See
Figure
Intel 5000P Chipset MCH implementation of SRID and CRID Registers
CCR - Class Code Register
This register contains the Class Code for the device. Writes to this register have
no effect.
Device
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
23:16
Bit
a
3-3.
:0, 2-3, 9
Attr
RO
0
09h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
09h
Intel 5000Z Chipset
4-7
0
09h
Intel 5000P Chipset
16
0, 2
09h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
17
0
09h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
21
0
09h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
09h
Intel 5000P Chipset
Default
06h
Base Class.
This field indicates the general device category. For the MCH, this field is hardwired
to 06h, indicating it is a “Bridge Device”.
Major Rev Id Minor Rev Id
7
6
5
4
3
2
Description
1
0
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