NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 8

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

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Ballout and Package Information................................................................................. 423
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10.2
10.3
Ballout and Package Information................................................................................. 491
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5-10 Thermal Throttling with THRMHUNT=1................................................................ 319
5-11 Thermal Throttling with THRMHUNT=0................................................................ 319
5-12 Thermal Throttling Activation Algorithm .............................................................. 321
5-13 XAPIC Address Encoding ................................................................................... 328
5-14 PCI Express Hot-Plug Interrupt Flow................................................................... 336
5-15 MCH to Intel 631xESB/632xESB I/O Controller Hub
5-16 x4 PCI Express Bit Lane.................................................................................... 343
5-17 ESI and PCI Express Ports 2 and 3 ..................................................................... 344
5-18 MCH to Intel 631xESB/632xESB I/O Controller Hub Port Configurations .................. 345
PCI Express Ports ............................................................................................ 418
Register Definitions .......................................................................................... 418
System Management Bus Interfaces................................................................... 421
Intel 5000P Chipset MCH Ballout........................................................................ 423
Intel 5000V Chipset MCH Ballout........................................................................ 444
Package Information ........................................................................................ 486
Intel 5000Z Chipset MCH Ballout........................................................................ 491
Package Information ........................................................................................ 530
Intel 5000P Chipset System Block Diagram ...........................................................23
Power-Up .........................................................................................................38
PWRGOOD ........................................................................................................38
Hard Reset .......................................................................................................39
RESETI# Retriggering Limitations ........................................................................39
Simplest Power Good Distribution ........................................................................42
Basic System Reset Distribution...........................................................................42
Basic INIT# Distribution .....................................................................................42
Conceptual Intel 5000P Chipset MCH PCI Configuration Diagram ..............................48
Type 1 Configuration Address to PCI Address Mapping ............................................50
Intel 5000P Chipset MCH implementation of SRID and CRID Registers ......................79
PCI Express Configuration Space........................................................................ 104
PCI Express Hot-Plug Interrupt Flow................................................................... 156
FB-DIMM Reset Timing ..................................................................................... 226
Intel 5000P Chipset DMA Error/Channel Completion Interrupt Handling Flow............ 260
System Memory Address Map............................................................................ 276
Detailed Memory System Address Map ............................................................... 277
Interrupt /SMM Region ..................................................................................... 284
System I/O Address Space................................................................................ 294
System I/O Address Space................................................................................ 296
Minimum Two DIMM Configuration ..................................................................... 301
Next Two DIMM Upgrade Positions ..................................................................... 301
Single DIMM Operation Mode............................................................................. 302
Minimum Mirrored Mode Memory Configuration.................................................... 302
Mirrored Mode Next Upgrade ............................................................................. 303
FB-DIMM Channel Schematic............................................................................. 304
Connection of DIMM Serial I/O Signals................................................................ 310
Code Layout for Single-Channel Branches ........................................................... 313
Code Layout for Dual-Channel Branches ............................................................. 314
Enterprise South Bridge Interface ...................................................................... 340
Intel 5000P Chipset Clock and Reset Requirements ...............................................37
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet