NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 84

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.2.1
84
Each PAM Register controls one or two regions, typically 16 Kilobytes in size
PAM0 - Programmable Attribute Map Register 0
This register controls the read, write, and shadowing attributes of the BIOS area which
extends from 0F 0000h - 0F FFFFh.
Two bits are used to specify memory attributes for each memory segment. These bits
apply to both host accesses and PCI initiator accesses to the PAM areas. These
attributes are:
RE - Read Enable. When RE = 1, the CPU read accesses to the corresponding memory
segment are claimed by the MCH and directed to main memory. Conversely, when RE =
0, the host read accesses are directed to ESI (Intel 631xESB/632xESB I/O Controller
Hub) to be directed to the PCI bus.
WE - Write Enable. When WE = 1, the host write accesses to the corresponding
memory segment are claimed by the MCH and directed to main memory. Conversely,
when WE = 0, the host write accesses are directed to ESI (Intel 631xESB/632xESB I/O
Controller Hub) to be directed to the PCI bus.
The RE and WE attributes permit a memory segment to be Read Only, Write Only,
Read/Write, or disabled. For example, if a memory segment has RE = 1 and WE = 0,
the segment is Read Only.
Device:
Function:
Offset:
Version:
7:6
5:4
3:0
Bit
Attr
RW
RV
RV
16
0
59h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Default
00
00
0h
Reserved
ESIENABLE0: 0F0000-0FFFFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0F0000 to 0FFFFF.
Bit5 = Write enable, Bit4 = Read enable.
Encoding
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
Reserved
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Register Description