NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 86

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.2.4
86
PAM3 - Programmable Attribute Map Register 3
This register controls the read, write, and shadowing attributes of the BIOS areas which
extend from 0D 0000h - 0D 7FFFh.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
1:0
7:6
5:4
3:2
1:0
Bit
Bit
Attr
Attr
RW
RW
RW
RV
RV
16
0
5Bh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
0
5Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Default
Default
00
00
00
00
00
LOENABLE2: 0C8000-0CBFFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0C8000-0CBFFF.
Bit1 = Write enable, Bit0 = Read enable
Encoding
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
Reserved
ESIENABLE3: 0D 4000h - 0D 7FFFh Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0D 4000h -0D 7FFFh.
Bit5 = Write enable, Bit4 = Read enable.
Encoding
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
Reserved
LOENABLE3: 0D 0000h - 0D 3FFFh Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0D 0000h -0D 3FFFh.
Bit1 = Write enable, Bit0 = Read enable
Encoding
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Description
Description
Description
Register Description